This chapter is about model, design, and application specific integrated circuit (ASIC) implementation to optimize turbo decoder using standard cell library of complementary metal oxide semiconductor (CMOS). Various constraints like channel noise, number of iterations, and frame length performance are analyzed and estimated through reference models. Register transfer language (RTL) model for encoder and decoder is developed, simulated, and synthesized by hardware description language (HDL). The ASIC implementation with various performance parameters like power and speed are considered to evaluate the proposed algorithm on decoder blocks. In the proposed low power turbo decoder, novel techniques like clock gating and adaptable iteration methods are used. This work proved the energy efficiency through elimination of unwanted iteration and early stopping mechanism. The results of the chapter are compared with other competent researches, and it shows that power dissipation is reduced by 34% with adaptable data rates for LTE standard wireless applications.
Top1.1 Introduction
The VLSI is abbreviated as Very Large-Scale Integration. In earlier days many forms of integration of more than 10000 transistors per chip were developed. This can be operating by specialized programming language. Also, they opened the way for ASIC designs, VLSI design flows and standard integrated circuits. These designs helped in revolutionizing the IC technology. The Figure 1 depicts the flow diagram of VLSI Design. The market design requirements are survey and the specifications are drafted for the problem. Once the specifications are drafted according to it the architectural design is done (Luo et al., 2017; Vargas et al., 2015). The logical and circuit design are completed. These designs are then simulated and verified if the simulation results are satisfied according to the specification then physical design will done. The steps involved in physical design are floorplan, placement, routing, and clock tree synthesis. After physical design the physical verification is done. If the results are obtained properly then the fabrication of the chip will be done after fabrication before going into the market it has to be packed and tested (Gladwin, 2018; Zhang & Li, 2011).
VLSI designs are successful, continuous efforts are put for improvements and advancements in increasing the number of transistors per chip in the area of VLSI. This leads to another technology called ultra VLSI technologies. The VLSI design is used to minimize the parameters like power consumption, process variations and so on (Calabuig et al., 2015; Saito, 2016).
VHDL is acronym of Very high-speed IC Hardware Description Language. It is used in EDA (Electronic Design Automation) to give the description of digital units such as FPGA and integrated circuits. Any VLSI design follows two different implementation methodologies, first one is top-down design approach, second is bottom-up design approach. In top-down approach, top module has the integrated sub modules and each sub module consists of leaf cells (Dai et al., 2012; Karim & Chakrabarti, 2010; Li et al., 2013). Here leaf cells cannot be divided further and these cells are gate level cells. In bottom-up approach, from the functional cells like gates to sub module then sub module to top module is integrated to follow the methodology. First, it entitles the description of structure of the system, i.e., how a system is disintegrated into sub-systems and how these sub-systems are concatenated (Karim & Chakrabarti, 2011; Roth et al., 2014; Shrestha & Paily, 2014). Second, it allows specification of the function of the system so that the designer knows what to do. Thirdly, it defines the detailed structure of the system to be designed.
A Field-programmable Gate Array (FPGA) is a homogeneous circuit design to be organized by the design engineer after fabricating. The structure of FPGA is predominantly uses a specified HDL language and any logical function can be implemented using FPGAs. FPGA consists of programmable logic units such as Configurable Logical Blocks (CLB). The CLBs are active functional blocks and are used to create the schematic from the Verilog HDL program (Broich, 2014; Lin, 2015; Manjunatha & Lohith Kumar, 2011). CLBs are connected through a reconfigurable interlink or fuse like material that allow the section to be connected together. This makes a path to establish between from input to output. It is like numerous logic gates uses different configuration for interconnection using wires. The simple and complex conjunctional functions are accomplished by configuring the logical blocks (Gladwin, 2018). In most of the FPGAs, the logical blocks also include memory elements or blocks of memory. The Figure 2 depicts overview of FPGA board.
Figure 2. Field Programmable Gate Arrays board