Designing a DC-DC Buck Converter in CMOS 180nm Technology

Abstract

This chapter presents the DC/DC buck converter and the two commonly control modes (pulse width modulation (PWM) voltage mode control and PWM current mode control). After the theoretical approach, the authors used Cadence Virtuoso 180nm process to design a buck converter that step down from 3.3 V to 1.8 V and with a load current of 500 mA. And to make the feedback control loop effects clear, they compared between those three architectures. With this comparison, they concluded that the CMC buck converter, although difficult to design, gave better results, with an output voltage of 1.84 V and a load current of 514 mA. The settling time is 41 us with a of power efficiency of 81%.