Distributed Selection of the Optimal Sizes of Analog Unity Gain Cells by Fuzzy Set Intersection

Distributed Selection of the Optimal Sizes of Analog Unity Gain Cells by Fuzzy Set Intersection

Said Polanco-Martagón (CENIDET, Mexico), Gerardo Reyes Salgado (CENIDET, Mexico), Georgina Flores Becerra (Instituto Tecnologico de Puebla, Mexico) and Esteban Tlelo Cuautle (INAOE, Mexico)
DOI: 10.4018/978-1-4666-6627-6.ch008
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A distributed system based on Fuzzy sets to select the optimal sizes of Unity Gain Cells (UGCs) is introduced. A zoom technique is also introduced to search for the optimal sizes in a more refined way. The selected sizes accomplish target specifications established by linguistic variables, namely gain “closer to” unity and “large” bandwidth, which are represented by fuzzy sets. The case of study is focused on three Voltage Follower and a CFOA whose performance characteristics are evaluated by using IC technology of 0.35µm and 180µm, respectively, and the circuit simulation program SPICE. Every circuit is codified by the width and large (W/L) of every Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) and by its bias current source. From the population of feasible solutions computed by evolutionary algorithms, the optimal W/L sizes are selected by the proposed distributed system through the intersection of fuzzy sets.
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Analog integrated circuit (IC) design using metal-oxide-semiconductor field-effect-transistors (MOSFETs) imposes challenges in sizing and selecting the right circuit topology (Tlelo-Cuautle 2011, 2013) because a huge plethora of active devices exist (Sánchez-López, Fernandez, Tlelo-Cuautle, & Tan, 2011; Sánchez-López, Martínez-Romero, & Tlelo-Cuautle, 2011). Each kind of active device provides different electrical characteristics, and then the same circuit under design may behave a little bit different using different active devices (Muñoz-Pacheco, Campos-Lopez, Tlelo-Cuautle, & Sánchez-López, 2012). Besides, all kinds of active devices find applications in analog signal processing (Muñoz-Pacheco et al., 2012; Pathak, Singh, & Senani, 2011; Swamy, 2011; Trejo-Guerra, Tlelo-Cuautle, Jiménez-Fuentes, Muñoz-Pacheco, & Sánchez-López, 2013).

To enhance the performances of the analog circuits, an analog IC designer should determine the optimal width (W) and length (L) of the MOSFETs. The problem of choosing the right circuit topology is known as circuit synthesis(Tlelo-Cuautle, 2011, 2013; Duarte-Villaseñor, Tlelo-Cuautle, & de la Fraga, 2012), and it is accompanied of a sizing procedure. In that case, the selected topology must accomplish a specific function which best behavior is performed by appropriate (W/L) sizing of its circuits elements. Thus, the sizing problem is related to finding the optimal width and length (W/L) values of the MOSFETs through an evaluation of multi-objectives (Zitzler, Thiele, & Bader, 2010) (performance parameters), for which heuristic algorithms (Graeb, Mueller-Gritschneder, & Schlichtmann, 2009; Olensek, Bürmen, Puhan, & Tuma, 2009; Fakhfakh, Cooren, Sallem, Loulou, & Siarry, 2010; Tlelo-Cuautle et al., 2010; Yaman & Yilmaz, 2010; Tlelo-Cuautle et al., 2011; Bernábe-Loranca, Coello-Coello, & Osorio-Lama, 2012; Hamadneh, Sathasivam, Tilahun, & Choon, 2012; Polanco-Martagón et al., 2012) create populations of feasible solutions approximating a Pareto front (Castro-López, Roca, & Fernández, 2009; Graeb et al., 2009) to guarantee optimal performance of active filters, oscillators, sensor conditioning circuits and so on (Pathak et al., 2011; Swamy, 2011; Khateb & Biolek, 2011; Campos-Canton, 2011). Hence, the selection of optimal sizes remains an open problem (Massier, Graeb, & Schlichtmann, 2008; McConaghy & Gielen, 2009; Olensek et al., 2009; Guerra-Gómez, Tlelo-Cuautle, & de la Fraga, 2013; Tlelo-Cuautle et al., 2011; Duarte-Villaseñor et al., 2012; Tlelo-Cuautle, 2013) given that are required multiple iterations of simulations (normally SPICE simulations) and parameter adjustments to accomplish target design specifications which guarantee the best performance of an analog IC. Therefore, in this chapter we introduce a distributed system based on fuzzy sets intersection for selecting the optimal sizes of analog ICs.

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