Dynamic Reconfiguration for Internal Monitoring Services

Dynamic Reconfiguration for Internal Monitoring Services

Julio Daniel Dondo Gazzano (University of Castilla – La Mancha, Spain), Fernando Rincon Calle (University of Castilla – La Mancha, Spain), Julian Caba (University of Castilla – La Mancha, Spain), David de la Fuente (University of Castilla – La Mancha, Spain) and Jesus Barba Romero (University of Castilla – La Mancha, Spain)
DOI: 10.4018/978-1-5225-0299-9.ch006
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Abstract

In hardware design flow, testing is the most important step to hardware quality assurance before a hardware component is released. However simulation and verification during design steps are not enough to guarantee a system without failures. In many cases the system fails after have been deployed. Dynamically reconfigurable FPGAs have the ability to reconfigure part of its architecture during run time without stopping the whole system. This feature is an added value that can be exploited for internal system monitoring and verification. Using partial reconfiguration, an Internal Monitoring System can be implemented in reconfigurable areas for monitoring different conditions and signals in the circuit, after implementation. This allows detecting and identifying those failures that were not possible to detect during simulation process.
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Introduction

The hardware design flow has been improved by the use of high-level languages and high-level synthesis tools, raising the level of abstraction and providing a fast and direct flow to a programmable device without the need to manually create RTL code. Most modern design suites include high-level synthesis (HLS) feature, reducing the complexity and allowing the automatic creation of advanced algorithms (A. Canis, J. Choi, M. Aldham, & V.Zhang, 2013).

HLS allows designers to describe functionality in a high-level programming language, such as C, C++ or SystemC, and translates it into low-level cycle-accurate RTL specifications for efficient implementation onto Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs). This synthesis can be optimized taking into account the performance, power, resources, etc. (Cong, B. Liu, S. Neuendorffer, J. Noguera, k. Vissers, & Z. Zhang, 2011). This kind of tools provides several advantages: better throughput, tolerant to changes, greater economic benefits and lower time-to-market (M. Santarini, 2012)

However, the verification step remains a hard task, and most verification scenarios include third-party components, such as memory or other hardware components.

The verification step is the bottleneck of most designs where roughly 70 to 80 percent of the design cycle is spent during the functional verification, driving to important economic losses for companies (H. Foster, 2013). The verification process is the most important step of a product life cycle, due to the reliability, quality and throughput of design production.

The hardware design process in FPGAs is involved in many simulations stages from pre-synthesised design to after-implementation simulation. But the final test is performed when the system have been deployed. It is very common to have failures conditions that can’t be detected during simulation.

One way to improve substantially the verification process is using Internal Monitoring System (IMS) components created to verify implemented designs in FPGAs, which can be deployed in a reconfigurable area, and that can be removed after completion of the design verification process. Using FPGA-based instrumentation, the verification and monitoring processes can be performed in a customized manner that exceed for far the classical instrumentation you can find in laboratories. Several instruments for internal monitoring and verification to face with specific problems or failures can be developed and implemented in the reconfigurable areas and be swapped in and out on-the-fly, according to the monitoring demand.

This proposal allows designers:

  • To check certain specific condition of the behaviour of a design, for example to check a sequence of signals or determined values that can happen once deployed and not only in simulation.

  • To detect a specific failure condition.

  • To detect a specific value in the bus or sequence of values once system have been deployed.

  • To observe, detect or register memory access to a specific address.

  • To collect information about bus addressing, to detect external or non-proprietary intrusion.

  • To check for intruders in Ethernet communication.

The use of dynamic reconfiguration capability in FPGAs has opened a new perspective in hardware design. Electronic digital circuits can be implemented in a way that permits the modification or replacement of some components on-the-fly, without stopping the whole implemented circuit. This feature can be exploited to develop very interesting mechanisms for internal system monitoring and verification.

Dynamic reconfiguration permits isolate those regions of the FPGA in which the modifications have to be introduced from those ones that remain unaltered.

Dynamic and Partial Reconfiguration extends the inherent flexibility of the FPGA, since it only modifies specific elements in the dynamic region at run-time, without stopping the rest of modules of the device. Therefore, this feature fits perfectly with the demands of adaptable and scalable solutions and is very convenient for all those applications that require real-time adaptability (V. Viswanathan, R.B. Atitallah, & J.L. Dekeyser, 2012).

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