Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

Mário P. Véstias (INESC-ID/ISEL/IPL, Portugal) and Horácio C. Neto (INESC-ID/IST/UTL, Portugal)
DOI: 10.4018/978-1-61520-807-4.ch002
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Abstract

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.
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Introduction

The increasing density of integrated circuits allows the implementation of systems-on-chip (SoC) with hundreds of homogeneous or heterogeneous processing and memory units. The communication between these units may become intensive requiring high bandwidth, low latency, quality of service to guarantee real-time functionality, and low power consumption. These requirements and constraints must be guaranteed by the communication infrastructure.

Traditional interconnection architectures, such as single buses or a hierarchy of buses, are no longer able to support the increasing interconnection complexity and the bandwidth demands of such platforms due to their poor scalability and shared bandwidth. The Network-on-Chip (NoC) communication structure has been introduced as a new interconnection paradigm able to integrate a significant number of IP cores while keeping a high communication bandwidth between them (Hemani et al., 2000; Dally & Towles, 2001).

Networks-on-Chip are becoming definitely the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC) for several reasons: (1) hundreds of IP cores can be “easily” integrated in a single device since NoC structures are scalable and do not have the problems associated with hierarchical bus structures which are usually irregular and harder to route; (2) lower design effort since a specific technological NoC solution can be easily scaled up, that is, designers do it once for each technology; (3) permits modular design with a hierarchy of communication layers that hide the inherent complexity of lower levels; and (4) robust designs can be achieved with fault tolerance using multi-paths for the same source-destination pair.

The first generation of NoC solutions considers regular topologies, typically 2D meshes under the assumption that the wires’ layout is well structured in such topologies. Routers and network interfaces between IP cores and routers are mainly homogeneous so that they can be easily scaled up and facilitate modular design. All advantages of a NoC infrastructure were proven with this first generation of NoC solutions.

However, soon, the designers started to be worried about the two main disadvantages associated with NoCs, namely, area and speed overhead. Routers of a NoC need space for buffers, routing tables, switching circuit and controllers. On the other side, direct bus connection is always faster than pipelined connections through one or more routers since these introduce latency due to packaging, routing, switching and buffering.

In a first attempt to consider area and latency in the design process, designers considered that regular NoC structures may probably be adequate for general-purpose computing where processing and data communication are relatively equally distributed among all processing units and traffic characteristics cannot be predicted at design time. But, many systems developed for a specific class of applications exhibit an intrinsic heterogeneous traffic behavior. Since routers introduce a relative area overhead and increase the average communication latency, considering a homogenous structure for a specific traffic scenario is definitely a waste of resources, a communication performance degradation and an excessive power consumption.

Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed to eliminate bottlenecks (Benini & De Micheli, 2002), with sized communication resources to reduce area utilization, and low latency wherever this is a concern. More, a specific component of the infrastructure can be complemented with some capabilities to deal with, for example, quality of service.

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