Dynamically Reconfigurable NoC for Future Heterogeneous Multi-core Architectures

Dynamically Reconfigurable NoC for Future Heterogeneous Multi-core Architectures

Balal Ahmad (Government College University, Pakistan & University of Edinburgh, UK), Ali Ahmadinia (Glasgow Caledonian University, UK & University of Edinburgh, UK) and Tughrul Arslan (University of Edinburgh, UK)
DOI: 10.4018/978-1-61520-807-4.ch010
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Abstract

To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard. This makes drNoC a highly re-useable communication framework, qualifying it as a communication centric platform for high data intensive SoC architectures. Simulation results show a 32% increase in data throughput and 22-35% decrease in network delay when compared with a traditional NoC with fixed parameters.
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History Of Drnoc

NoC has been under the spotlight since it was first introduced and many research groups are working on different aspects of NoC design. (Hemani et al., 2000) proposed a packet switched architecture with switches surrounded by six resources and connected to 6 neighbouring switches. The architecture was called honeycomb due to the hexagon based pattern of switches and resources. The concept of packet switching re-appeared in other consecutive approaches but the topology simplified in most proposals to a mesh of resources and switches (Guerrier and Greiner, 2000).

(Dally and Towles, 2001) proposed replacing global wiring with a general purpose on chip interconnection network at an area overhead of 6.6%. A 12mm×12mm chip in 0.1µm CMOS technology was developed. Dally concluded that there can be up to 6,000 wires on each metal layer crossing each edge of a tile(3mm×3mm). It is quite easy to achieve over 24,000 ‘pins’ crossing the four edges of a tile. By effectively choosing the network topology these abundant wiring resources can be converted into bandwidth.

(Benini and Micheli, 2002) proposed a layered design methodology borrowing models, techniques and tools from the network design field and applying them to SoC design. Several open problems at various layers of the communication stack were addressed and a basic strategy was given to effectively tackle them for energy efficient design. Xpipes compiler was also presented as a tool for automatically instantiating an application specific NoC for heterogeneous multi-processor SoCs.

(Kumar et al. 2002; Sun, Kumar and Jantsch, 2002) constructed a model of NoC using a public domain network simulator NS-2 and evaluated design options for a specific NoC architecture which has a two dimensional mesh of switches. S. Kumar analysed the series of simulation results to determine the relationship between buffer size in switch, communication load, packet delay and packet drop probability. The results are useful for the design of an appropriate switch for the NoC.

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