Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

Efficiency Analysis of Approaches for Temperature Management and Task Mapping in Networks-on-Chip

Tim Wegner (University of Rostock, Germany), Martin Gag (University of Rostock, Germany) and Dirk Timmermann (University of Rostock, Germany)
DOI: 10.4018/978-1-4666-6034-2.ch015
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With the progress of deep submicron technology, power consumption and temperature-related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management and task mapping. On the other hand, application of according thermal-aware approaches is accompanied by disturbance of system integrity and degradation of system performance. In this chapter, a method to predict and proactively manage the on-chip temperature distribution of systems based on Networks-on-Chip (NoCs) is proposed. Thereby, traditional reactive approaches for thermal management and task mapping can be replaced. This results in shorter response times for the application of management measures and therefore in a reduction of temperature and thermal imbalances and causes less impairment of system performance. The systematic analysis of simulations conducted for NoC sizes up to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile. Similar effects can be observed for proactive thermal-aware task mapping at system runtime allowing for the consideration of prospective thermal conditions during the mapping process.
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The emergence of nanotechnology is accompanied by cumulative power densities and switching activities per unit area. Therefore, increasingly complex and highly integrated systems like SoCs have to contend with well-known challenges. Amongst others, this concerns heat dissipation, leading to high circuit temperatures and possibly strongly unbalanced on-chip temperature distributions (see ∆T [°C] in Table 2 for examples regarding on-chip temperature variations). In the light of a growing number of transistors per chip, which are increasingly susceptible to environmental influences and deterioration, this issue is topical more than ever. As a consequence, thermal stress and physical effects exponentially depending on temperature (JEDEC, 2009) threaten the integrity of Integrated Circuits (ICs) and have major influence on operability, lifetime and performance.

Table 2.
Router delay DR, delay of packet delivery DP, net data throughput DataNet, the number of delivered packets PTrans, average temperature TAvg, the peak temperature difference ∆T and the maximum temperature TMax for reference systems of different size
DR [cycles]556
DP [cycles]283238
DataNet [bit/cycle]2861113
PTrans [# in million]50.4109.8201.7
TAvg [°C]58.565.571.9
∆T [°C]11.422.830.4
TMax [°C]67.684.896.7

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