Electronic Hardware for Fuzzy Computation

Introduction

Electronic hardware development for fuzzy inference-based computing systems (fuzzy hardware) has been an active research area almost since the first papers on successful fuzzy logic applications, mainly fuzzy controllers, were published in the early eighties. Although historically, due to the greater flexibility and compatibility, as well as the advantages and easiness of using high level languages, the majority of fuzzy inference system (FIS) implementations have been software developments to be run on general purpose processors (GPP), only concurrent computation architectures with specific processing units can take greatest advantage of fuzzy computation schemes. The development of fuzzy hardware has been mainly motivated by real-time operation demands, or by low power and/or small area occupation requirements. In this sense, the first fuzzy hardware researchers basically tried to design fuzzy chips capable of processing fuzzy control laws in a more efficient manner in terms of processing speed, occupied area and consumed power. But not only is computing efficiency a concern for fuzzy hardware designers; system programmability, compatibility of input/output signals and scalability at various levels (word-length, partition of the input and output domains, number of rules, or overall throughput gain) are also important features to be considered.

Design of fuzzy hardware is strongly conditioned by the target application it is addressed to. In consequence, many different application-specific designs have been reported, each of them showing characteristic features, strengths and weaknesses. The choice of the development platform and implementation technology is closely linked with this issue, and may itself bias the obtainable final features. Despite this, implementation of a general purpose fuzzy ASIC (Application Specific Integrated Circuit) suitable for any fuzzy rule-based application has been somehow sought but never achieved by fuzzy hardware designers, both in academic and in commercial contexts. It has been the arrival of high capacity reconfigurable hardware and the drastic changes in the design processes of complex digital systems associated with this technology that has finally made obsolete the general purpose fuzzy hardware objective. Last generation reconfigurable hardware platforms allow the implementation of optimized complex hardware/software codesigned adaptive and on-the-fly reconfigurable systems for application specific computation. The combination of reconfigurable hardware with the use of standardized hardware description languages (HDL) has entailed the transference of the task of achieving desirable features such as flexibility, scalability, reusability, etc from the hardware itself to the description or modeling of this hardware.

Fuzzy data management and analysis methods do not rest normally on a rule-based inference scheme, so the development of hardware for fuzzy data-mining has usually little to do with what is referred to as “fuzzy hardware”. In fact, fuzzy data-mining algorithms have been traditionally implemented by software applications running on GPPs, since there were not usually tight requirements for computation time, occupied silicon area or consumed power. On the contrary, flexibility, scalability and good interaction with data base storage systems were the only concerns. Nonetheless, nowadays, due to the increasing complexity of data-mining algorithms and the growing amount of data to be processed by them, sometimes with time constraints, more attention is being paid to the hardware acceleration of this kind of application. This field can be considered, together with scientific computation, a natural target for high performance computing (HPC). Consequently, specific hardware development for parallel processing or coprocessing of data-mining algorithms has been gaining relevance in recent years.