Enhancing an Automatic Analog IC Design Flow by Using a Technology-Independent Module Generator

Enhancing an Automatic Analog IC Design Flow by Using a Technology-Independent Module Generator

António Canelas, Ricardo Martins, Ricardo Póvoa, Nuno Lourenço, Jorge Guilherme, Nuno Horta
DOI: 10.4018/978-1-4666-6627-6.ch005
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This chapter presents a new methodology to enhance the optimization process of an analog integrated circuit synthesis tool, AIDA-C, by taking into account the floorplan of the circuit. The addition of the new Analog Module Generator (AMG) in the AIDA framework creates the possibility to efficiently explore the circuit floorplan during the optimization process and to improve the quality of the final floorplan by adding complex device structures enhancing the layout matching, symmetry, and routing, reducing some of the non-idealities to which analog integrated circuits are so sensitive. The performance enhancement attained with AMG is demonstrated using a well-known benchmark circuit, optimized by AIDA-C with and without taking into account AMG's complex structures in the evaluation of the circuit's floorplan.
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The increase in device density on today’s integrated circuits (IC), resulting from CMOS shrinking process into smaller nanometer-scales, creates new challenges in the IC design process and particularly to electronic design automation tools (EDA). The approach adopted on systems-on-a-chip (SoC) (Gielen, 2007), where a digital circuit and an analog section coexist on the same die, reveals the higher complexity of the designing process of the analog circuit in comparison to the digital counterpart, where the lack of effective EDA tools for the analog circuit design flow (Rutenbar, 2010) is one of the main reasons for the larger design cycle of the analog blocks. The circuit sizing process is one the first tasks in the analog IC design flow, whose automation is, usually, achieved with the help of optimization-based techniques. Several of these techniques, evaluate the performance of the solutions during the optimization process using circuit simulators, like in (Castro-Lopes, Guerra, Roce, & Fernandez, 2008), (Lourenço & Horta, 2012) or (McConaghy, Palmers, & Gielen, 2011); a different approach, using equations to save the simulation time is taken by (Chen, Ding, Liao, Chang, & Liu, 2013) where several analog IP’s are retarget and reused in new projects.

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