Green Semicondoctor Design Techniques and Challanges

Overview

To build environment friendly electronics devices low power design techniques have vast application and scope in coming era, low power designs are going to dominate not only electronics world but all product design sectors. To build digital low power systems we have to start planning at the Register transfer level (RTL) coding itself, for saving power at Register transfer level (RTL) use below mentioned techniques, you can find more details about these techniques in references section provided on last page of this chapter.

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  Early Power estimation. (www.fijutsu.com)

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  Multi power source design technology reduces power consumption while active. (Mayo, N. & Ranganathan, P., 2005)

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  Combinational clock gating reduces power consummation while idle.

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  Sequential clock gating reduces power consumption while idle.

Early Power Estimation

Early power estimation is always the preferred one because if after finishing the system design we founding that system is exceeding power budget then all money and efforts put on designing that system will be waste. That’s why always do power estimation before starting the design. Now question is how we can do early power estimation or how can we define power consumption threshold limit for a System on chip (SOC) targeted for ASIC or FPGA? It is possible to calculate approximate power consumption number for both ASIC and FPGA targeted System on chip (SOC) designs at design architecture stage. The estimated power will help us in defining thresholds limits for power utilization by SOC. For ASIC rough estimation of gate count (Approximate digital gate count, Power requirement of analog blocks and other ready to use IP cores) and power calculation parameter provided by target technology vendor will be utilized to calculate approximate power consumption for ASIC targeted SOC. Early power estimation for FPGA is similar to ASIC but here life is bit easy and which gives us lots of choice in selection of target FPGA device, most of FPGA vendors use to provide power calculation excel sheets (For example Xilinx, we can go to www.xilinx.com and download early power estimation excel sheets free of costs) where we have to enter rough estimation of gate count numbers like in case of ASIC and select targeted FPGA device which meets basic requirements like which meets frequency and silicon size requirement of our SOC. By using early power estimation excel sheets of different vendor not only we will do approximate power estimation of our SOC but after comparing their results we can finalize a FPGA device which is also a cost effective solution for our SOC. Now the question is how early power estimation will help us in designing a low power solution? After doing early power estimation of our SOC architecture we know two very important points one how far we are from boundaries of our power budget, second our SOC architecture is a feasible solution or not in terms of cost and power requirements market is excepting. Once we know these two things and found that we are in a range of 5-8% away from market needs then we can move towards micro architecture of design because in this range after doing a good logic design optimization and after applying clock gating we can meet our power budget. In case our estimated power is 5-8% above market needs then it’s always better to go back and change your SOC design architecture.