Green Semicondoctor Design Techniques and Challanges

Green Semicondoctor Design Techniques and Challanges

Somesh Rajain (eInfochips Pvt. Ltd., India), Chetan Shingala (Sibridge Technologies Ltd, India) and Ekata Mehul (eInfochips Pvt. Ltd., India)
DOI: 10.4018/978-1-60960-472-1.ch210


The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.
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To build environment friendly electronics devices low power design techniques have vast application and scope in coming era, low power designs are going to dominate not only electronics world but all product design sectors. To build digital low power systems we have to start planning at the Register transfer level (RTL) coding itself, for saving power at Register transfer level (RTL) use below mentioned techniques, you can find more details about these techniques in references section provided on last page of this chapter.

  • Early Power estimation. (

  • Multi power source design technology reduces power consumption while active. (Mayo, N. & Ranganathan, P., 2005)

  • Combinational clock gating reduces power consummation while idle.

  • Sequential clock gating reduces power consumption while idle.

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