Wireless Sensor Networks (WSNs) are currently attracting great interest and the number of its application domains is varying and increasing. However, some of these applications are very sensitive to the execution time and require huge memory and computation resources, which contrast to the nature of sensor motes with limited capabilities. There have been a lot of software solutions that aim to optimize the memory consumption and to reduce the execution time of WSN applications, but few previous research efforts considered a hardware/software optimization of the sensor mote resources. The limitation of studies on hardware optimization on WSN motivated the authors to write this chapter, with the objective to design a new HW architecture with FPGA technology that allows extending the sensor mote capabilities. An optimal routing protocol to efficiently route messages between motes was chosen. It enables the reduction of different communication problems such as message unreachability, long paths, and traffic congestion. The authors first study one of WSN applications that require great resources, image processing. They demonstrate how the memory and processing capabilities of classical sensor motes are not sufficient for the treatment of this application, and the point-to-point routing cannot be applied in such applications. The authors then survey the most important routing protocols for WSNs in order to select the best routing algorithm. They finally propose a reconfigurable HW/SW architecture based on FPGA for critical WSN applications. Results show that the proposed solution outperforms the performance of the classical sensor motes, and is extensible for application to other WSN applications.
TopIntroduction
During the last few years, the use of embedded systems and System on Chip (SoC) has massively grown. Hence, time and cost are key factors in the success of these products in the competitive electronics marketplace.
Wireless Sensor Networks which integrate a SoC are becoming a necessity in our daily life reminding its different covered areas. Sensor Networks have been deployed for a variety of applications, including environment monitoring, health-care monitoring, transportation systems, home automation, etc. (Mainwaring et al., 2002).The evolution of applications provided by these systems has spawned related problems like complexity and sensitivity.
The Discrete Wavelet Transforms (DWT) have been extensively used in many digital signal processing applications.
The design of a SoC, which integrates this kind of application, causes a lot of constraints like minimizing the time to market, the cost and energy consumption. Therefore, designers had to reduce the development time, to validate the designed system and to ensure its efficient functioning (Janapsatya, Ignjatovi, & Parameswaran, 2006).
Choosing the appropriate embedded processor, which will be integrated in the SoC to implement DWT, is an essential step. The advantage of using embedded softcores processor is their higher flexibility and easier configuration than hardcores.
In this work, a softcore embedded processor has been adopted in order to adapt its architecture as required by DWT using the Algorithm Architecture Adequacy (AAA) approach (Liu, Tanougast, & Weber, 2006)
The objective of this study is to integrate DWT on a chip using an embedded processor while increasing processing speed and minimizing costs. The Implementation of DWT in WSN is presented in Figure 1.
Figure 1. Implementation of DWT in WSN
Virtual prototyping is an interesting designing method which allows the designer to validate the design before Hardware implantation. Modelsim software was used to simulate the program running and to determine its execution time. A hardware/Software implementation on FPGA was also done and performance was measured. A literature review of the existing routing protocols for WSNs was provided (Chakeresa & Klein-Berndtb, 2002; Perkins & Belding-Royer& Das, 2003; Erge, 2004; Kim & Montenegro, 2007). After then, they are compared in terms of energy consumption and memory overhead in order to choose the best routing protocol for the proposed solution.
The remainder of this chapter is organized as follows. First, First, the background and the related work in WSN, DWT, and SOC process cores are discussed in Section 1. Section 2 deals with problems of DWT implementation in WSNs. Section 3 presents HW/SW implementation of DWT using an embedded processor core. Section 4 describes the choice of the routing protocol for the proposed system. Finally, we conclude and give some perspectives in Section 5.