Hardware Virtualization on Dynamically Reconfigurable Processors

Hardware Virtualization on Dynamically Reconfigurable Processors

Christian Plessl (University of Paderborn, Germany) and Marco Platzner (University of Paderborn, Germany)
DOI: 10.4018/978-1-60960-086-0.ch004
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Numerous research efforts in reconfigurable embedded processors have shown that augmenting a CPU core with a coarse-grained reconfigurable array for application-specific hardware acceleration can greatly increase performance and energy-efficiency. The traditional execution model for such reconfigurable co-processors however requires the accelerated function to fit onto the reconfigurable array as a whole, which restricts the applicability to rather small functions. In the authors’ research presented in this chapter, the authors have studied hardware virtualization approaches that overcome this restriction by leveraging dynamic reconfiguration. They present two different hardware virtualization methods, virtualized execution and temporal partitioning, and introduce the Zippy reconfigurable processor architecture that has been designed with specific hardware virtualization support. Further, the authors outline the corresponding hardware and software tool flows. Finally, the authors demonstrate the potential provided by hardware virtualization with two case studies and discuss directions for future research.
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The design and implementation of embedded systems is generally challenging due to the stringent performance, power and cost constraints. It has been shown for many applications that co-processors based on field-programmable reconfigurable hardware devices, such as FPGAs, allow for significant speedups, cost and energy savings over embedded systems based on general-purpose microprocessors or microcontrollers. However, mapping complete applications rather than kernels to a reconfigurable device is difficult and often inefficient. It is useful to offload the performance hungry and latency sensitive application kernels to a reconfigurable coprocessor, while relying on a comparatively simple CPU core for handling the system management and control tasks that are not performance critical. Hence a processor architecture that combines reconfigurable hardware with a general-purpose CPU core in an integrated device is an attractive platform for building embedded systems. These architectures, denoted as reconfigurable processors have received increasing attention in the last years and a number of architectures have been introduced both in academic research and in the commercial marketplace.

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