Hardware Virtualization on Dynamically Reconfigurable Processors

Background

The design and implementation of embedded systems is generally challenging due to the stringent performance, power and cost constraints. It has been shown for many applications that co-processors based on field-programmable reconfigurable hardware devices, such as FPGAs, allow for significant speedups, cost and energy savings over embedded systems based on general-purpose microprocessors or microcontrollers. However, mapping complete applications rather than kernels to a reconfigurable device is difficult and often inefficient. It is useful to offload the performance hungry and latency sensitive application kernels to a reconfigurable coprocessor, while relying on a comparatively simple CPU core for handling the system management and control tasks that are not performance critical. Hence a processor architecture that combines reconfigurable hardware with a general-purpose CPU core in an integrated device is an attractive platform for building embedded systems. These architectures, denoted as reconfigurable processors have received increasing attention in the last years and a number of architectures have been introduced both in academic research and in the commercial marketplace.