This Chapter addresses the above-mentioned challenges by presenting a holistic diagnosis approach for design error location and malicious fault list generation for soft errors. First, a method for locating design errors at the source-level of hardware description language code using the design representation of high-level decision diagrams is explained. Subsequently, this method is reduced to malicious fault list generation at the high-level. A minimized fault list is generated for optimizing the time to be spent on the fault injection run necessary for assessing designs vulnerability to soft-errors.
TopIntroduction
Designing a microelectronic chip is a very expensive task and excessive design costs are the greatest threat to continuation of the semiconductor industry’s growth (SIA, 2007). In order to contain this threat, the increasing gap between the complexity of new systems and the productivity of system design methods must be mitigated by developing new and more efficient design methods and tools. Functional correctness of systems is becoming ever more difficult to attain and it is becoming the main bottleneck in the systems’ development process. Better verification techniques must be the focus in research and development if we want to keep increasing the scale of electronics design. Detection of mistakes, however, offers only a partial solution to the correctness issue. Once that has been ascertained, the difficult task of discovering the sources of mistakes (faults) and subsequently locating and correcting them remains.
It is a well acknowledged fact that verification is forming a major part in the total product design cycle (Lam W. K., 2005) and this trend is increasing. At the same time when there have been numerous research works on verification methods identifying the occurrences of errors, the problem of diagnosing the causes of errors and correcting them has been largely neglected. Yet a large part of the verification cycle is consumed inside the design loops between debugging and correction. It is estimated that fault location and correction constitute roughly half of the total time spent on verification and debug (FP6 PROSYD, 2004). Verification and debug (i.e. assuring the correctness of the design), in turn, represent the main reason of the excessive costs accounting for about 70% of design expenses (Lam W. K., 2005). Location and correction costs therefore form about 1/3 of the total design time. Figure 1 visualizes the amount of time spent on specification, design, fault detection, location, and correction in a typical design process (FP6 PROSYD, 2004).
Figure 1. Time spent on different tasks in a design process
Design error diagnosis for combinational circuits has been thoroughly studied for two decades. There exist, both, fault model based (Madre, J. C., Coudert, O., & Billon, J. P. (1989); Abadir, M. S., Ferguson, J., & Kirkland, T. E. (1988)) and fault-model-free (Ali, M. F., Safarpour, S., Veneris, A., Abadir, M. S., & Drechsler, R., 2005) approaches. There have been attempts to generalize the above methods for sequential circuits (Ali, M. F., Safarpour, S., Veneris, A., Abadir, M. S., & Drechsler, R. (2005); Wahba, A., & Borrione D. (1995)), resulting in scalability problems. Some of the previous works support design error diagnosis for high-level models like the Register-Transfer Level (RTL) (Fey, G., Staber, S., Bloem, R., Drechsler, R. (2008); Chang, K.-h., Wagner, I., Bertacco, V., & Markov, I. (2007)). However, these methods rely on reducing the diagnosis to logic-level formal engines. Current chapter considers a different approach utilizing a source-level reasoning engine for the diagnosis process. In our case the engine operates on the model of register-transfer level decision diagrams. This results in RT-level feedback to the engineer and is therefore better understandable than logic-level debug information proposed by previous methods.