Input/Output Ports

Input/Output Ports

Copyright: © 2017 |Pages: 26
DOI: 10.4018/978-1-68318-000-5.ch006
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This chapter discusses the different I/O ports available on PIC18 microcontrollers. A detailed description of the underpinning hardware behind these ports as well as their features, limitations and applications will be covered. Figure 1 shows the pin diagram of PIC18F25K22/26K22 processors having 3 ports (PORTA, PORTB and PORTC) as well as PIC18F45K22/46K22 processors having as many as 5 ports (PORTA, PORTB, PORTC, PORTD and PORTE). Throughout the chapter, you need to refer to Appendix 2 for bit-by-bit description of special function registers as well as Appendix 7 (configuration registers).

Figure 1.

Pin diagram of PIC18F25K22/26K22 and PIC18F45K22/46K22



A parallel port such as PORTA allows the processor to interface with the outside world. It may be used both as input or output. When used as output, a port consists of a set of 8 flip-flops with the D-inputs connected to the data bus and the Q-outputs connected to the port pins. It is accessible via a write operation (e.g. movwf PORTA).

Similarly, data appearing on the input pins of a port may be acquired via a read operation (e.g. movf PORTA, W). Using a port pin both as input and output is illustrated in Figure 2. When the TRIS latch is cleared , the output buffer acts like a closed switch. This allows the data latch output be routed to the output pin.

A port pin is treated as a digital I/O pin if the corresponding bit in ANSEL register is 0. For instance, if RA2 (PORTA, bit 2) is to be used as a digital I/O pin, then ANSELA<2> (ANSELA register, bit 2) must be cleared. If not, this pin is treated as analog (default value) and is read as logic ‘0’. Table 1 lists the status of I/O pins for all different possibilities.

Figure 2.

Bit slice of PORTA; only RA<3:0> and RA5 may be used as analog.

When the pin is configured as input , the output buffer behaves like an open circuit. This isolates, electrically speaking, the data latch from the input pin and hence no data contention occurs. Electrical isolation is extended to the data bus as well. In fact, the control signals RD TRISA, RD LATA and RD PORTA allow only one input at a time to be fed to the data bus: , or (logic level of RAx) respectively.

Table 1.
Pin configuration of ports; applicable to ports A through E

Five of PORTA pins have a dual purpose: analog and digital. These pins are RA0/AN0, RA1/AN1, RA2/AN2, RA3/AN3 and RA5/AN4. Upon power-up reset, these pins are configured as analog inputs. The bits in charge of configuring PORTA pins as analog versus digital reside in ANSELA (see Table 2).

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