Leakage Minimization in CMOS VLSI Circuits: A Brief Review

Leakage Minimization in CMOS VLSI Circuits: A Brief Review

Saurabh Chaudhury (NIT Silchar, India) and Rohit Lorenzo (NIT Silchar, India)
Copyright: © 2016 |Pages: 29
DOI: 10.4018/978-1-5225-0190-9.ch004
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Abstract

Ever increasing demand for portable and battery-operated systems has lead to aggressive scaling. While technology scaling facilitates faster and high performance devices, at the same time it causes excessive power dissipation. Leakage power dissipation is now a dominating component of total power consumption in such portable devices. So there is a tremendous need to limit the power dissipation in high density chips which has initiated many innovative techniques to develop in the design of low power circuits and systems. Today's nano-scaled VLSI chips have ultra-thin gate oxide, very low threshold voltage and having short channels. As such leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. This Chapter review and compare the state of the art circuit techniques for leakage minimization. It also conceptually classifies the different techniques of leakage minimization. Moreover, a detailed comparison based on trading-offs with other design parameters is also given along with leakage minimization.
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1. Introduction

Modern digital integrated circuits (ICs) are characterized by high performances and higher packing densities. This is because of aggressive device scaling that is taking place in every generation of technology, which may continue for a few more years till the device physics continue to hold true. Higher integration is economically attractive because it leads to a reduction in number of components per system, thereby reducing the cost of interconnection and packaging. Moreover, it enhances the reliability of the overall system. Higher integration makes a circuit faster because of the reduction in parasitic effects in devices and interconnects. With the increasing growth of portable, battery-operated digital equipments, like, cell phone, laptop, personal digital assistant, multimedia products etc., power consumption has become one of the major design issues today, besides area, performance, cost and yield. On the other hand, life of battery is also limited. In spite of remarkable developments in battery technology, such as, high capacity rechargeable Lithium-ion cells, a revolutionary change in battery technology in near future also seems feeble. Under these circumstances, the only possibility to reduce power consumption is by adopting some innovative low power circuit design strategies. Moreover, unnecessary power dissipation, when the circuit or its constituent parts are inactive, has to be limited by dynamic power management schemes. When a circuit is optimized in terms of power, there are a lot of advantages. It helps to develop and use less expensive packaging and cooling, since core is less heated-up. This is essentially very important from the point of view of overall cost of the system and hence low power strategy is even applied now-a-days to desktop or workstation computers to reduce packaging and cooling cost.

To achieve low power, more emphasis is given in each level of the design cycle, starting from system or architectural level, down to the physical level. Economics of production, on the other hand, not only depends on volume of production but also on design styles, intended applications, time-to-market and quality of circuit design and fabrication. In reality, very few circuits enjoy large volume of sales and a long life, e.g. some general purpose processors, but unfortunately technology advancements make them obsolete in a short time. Application Specific Integrated Circuits (ASICs), on the other hand, are designed to perform some limited set of tasks, but they capture a large portion of the market share. Computer Aided Design (CAD) techniques play a vital role in circuit optimization for some specific quality and in the reduction of design time. As the level of integration is continually increasing (of the order of millions of devices in a single chip), the task of carrying out a complete design without errors is becoming increasingly difficult for human designers. The technological advancements in the field of electronics have resulted in more and more cores and processors that are being put on smaller System on Chip (SoC) (Kaur, 2013). These high performance systems are mostly power hungry. CAD tools have been used since the inception of integrated circuits. CAD techniques achieved a fairly good level of maturity in many areas by today and will continue to support designing increasingly larger circuits with its enhanced capabilities. In order to reduce power consumption, supply voltage is continually scaled down, as the dynamic or the switching power is directly proportional to square of the supply voltage. Scaling of power supply demands for scaling the threshold voltage also, to avoid any performance degradation. Leakage power is of no concern in long channel devices. Reduction in threshold voltage gives rise to more and more leakage power consumption as subthreshold leakage is exponentially dependent on threshold voltage. Subthreshold leakage dominates over all other leakages above 100 nm devices. For technologies below 90 nm, oxide leakage and band-to-band tunnelling leakage predominates. Leakage power consumption has become comparable to dynamic power consumption at recent technology level and even higher than dynamic power in many applications and hence need to be emphasized early in the design cycle over and above dynamic power. The increasing trend of power dissipation according to international technology roadmap for semiconductor (ITRS) (http//www.itrs.net) is depicted in Figure 1.

Figure 1.

ITRS power dissipation trend

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