Low Complexity Processor Designs for Energy-Efficient Security and Error Correction in Wireless Sensor Networks

Low Complexity Processor Designs for Energy-Efficient Security and Error Correction in Wireless Sensor Networks

J. H. Kong, J. J. Ong, L.-M. Ang, K. P. Seng
Copyright: © 2012 |Pages: 19
DOI: 10.4018/978-1-4666-0101-7.ch017
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Abstract

This chapter presents low complexity processor designs for energy-efficient security and error correction for implementation on wireless sensor networks (WSN). WSN nodes have limited resources in terms of hardware, memory, and battery life span. Small area hardware designs for encryption and error-correction modules are the most preferred approach to meet the stringent design area requirement. This chapter describes Minimal Instruction Set Computer (MISC) processor designs with a compact architecture and simple hardware components. The MISC is able to make use of a small area of the FPGA and provides a processor platform for security and error correction operations. In this chapter, two example applications, which are the Advance Encryption Standard (AES) and Reed Solomon (RS) algorithms, were implemented onto MISC. The MISC hardware architecture for AES and RS were designed and verified using the Handel-C hardware description language and implemented on a Xilinx Spartan-3 FPGA.
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Background

Ultimate Reduced Instruction Set Computer (URISC)

The URISC which was first proposed by (Mavaddat & Parhami, 1988) is meant for educational purpose. It has been an inspiration and insight to the CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer). This simplified model of computer architecture is flexible with only a single instruction incorporated can be further expanded and implemented on hardware easily. The URISC uses only one instruction called the SBN instruction (Subtract and Branch If Negative). By using only the SBN instruction, the URISC is able to perform data addition and subtraction. Logical operations can be performed to execute data movement from one location to another. The URISC consists of an Adder circuit as its sole ALU. Detailed operation of the URISC can be found in (Mavaddat & Parhami, 1988). Figure 1 shows the schematic of the URISC architecture.

Figure 1.

The URISC architecture

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The ‘Subtract and Branch if Negative’ (SBN) processor was first proposed by Van der Poel (Gilreath & Laplante, 2003). With this primitive SBN instruction, the URISC is built from its basic processor. The basic operations of URISC are moving operands to and from the memory, with addresses corresponding to the registers. The arithmetic computation can be performed and the results are stored in the 2nd operand’s memory location. Similarly, to execute URISC instructions, the Core subtracts the 1st operand from the 2nd operand, storing the results in the 2nd operand’s memory location. If the subtraction results a negative value, it will ‘jump’ to the target address, else, it proceeds to execute the next instruction in the following sequence (Gilreath & Laplante, 2003). Figure 2 shows the pseudo-code format of the SBN instruction written in programming.

Figure 2.

Pseudo-code format of the SBN instruction

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