The low power design for communication systems are in real demand for green information and communication technologies (ICT). It is observed that more than 35% of total power consumption in the world is utilized by ICT devices (Cetinkaya & Akan, 2015) (Yigit, Gungor, Tuna, Rangoussi, & Fadel, 2014). In this concern, saving of ICT devices power is now becoming a social responsibility. In this chapter, authors demonstrated the low-power design for VLSI based high-speed communication system using proposed IO Standard technique. The low power design of VLSI based high communication system is verified by implementing the designed system on 28 nm chip size packed in UltraScale FPGA device. The variation in proposed IO Standard technique varies the chip power and other chip parameters such as; temperature and other power consumption like; IO Power, logic power, clock power and etc. to produce the low power design for the VLSI based designed system. Furthermore, the designed VLSI based high speed communication system represents a springboard for developing future generation networks using proposed technique. The implementation of these system on UltraScale FPGA that deliver the affluence design with several low power features.
The chapter is organized by discussing the background of previous and currently used techniques to reduce the power consumption for VLSI design system. The basic terminologies related to the research work are also discussed to support the features of proposed technique. The methodology to develop the low power design for VLSI based high speed communication system is also discussed along with power. Finally, results and conclusion are discussed to define the output characteristics of low power VLSI based high speed communication system. This chapter will help the students, researcher and academicians for designing and implementing the low power VLSI based designed system on VLSI chip using UltraScale devices. The audience will enjoy the experience of interesting feature of low power design for VLSI based high speed communication system using proposed technique. Using proposed technique, several real time systems can be developed as a low power design.
Background
High-speed communication systems are the set of interconnected components that provide services to the users e.g. information services for near and far reach and other in (Mendez et al., 2014). In high-speed communication system, the thermal excoriation in components and other power challenges indulge extra cost (Whitfield & Doyel, 1984) (Cloetens, 2014) for the system. There are several techniques involved in developing low power design for the components (Wenger, 2014). One convenient and easy solution for all above problems is to design low power VLSI design using hardware descriptive language (HDL) or Verilog HDL (VHDL) (Verhelst et al., 2015). Formerly, the primary concerns of Very Large Scale Integration (VLSI) designers was to improve the area, cost and reliability of design; power consumption was secondary like other parameters (Mahoob & Mehra, 2015). Nevertheless, power consumption issue is dealt as primary issue to be solved for different systems. The numerous studies have contributed in this regard (Hinton, Jalali, & Matin, 2015). The power reduction can be accomplished through several available techniques e.g. clock gating (Sahni, Rawat, Pandey, & Ahmad, 2015), voltage scaling (Li , Xie, Wang, Nazarian, & Pedram, 2015) (Chandrakasan, Sheng, & Brodersen, 1992), variable frequency (Chandrakasan & Brodersen, 2012). Moreover, variable power supply (Gonzalez, Gordon, & Horowitz, 1997), multiplied threshold (Ghosh & Ledwich, 2012), chip reduction and packaging size (Tummala, Rymaszewski, & Klopfenstein, 2012), design improving techniques, power management techniques (Seo, Lee, Lee, & Kang, 2015) are also used for low power design. In (Yadav & Pandey, 2015) designed the low power half adder cell using threshold based CMOS design. (Xu, Gu, Wu, & Chang, 2015) developed the 140 GHz transmitter using CMOS for data rate of 2.5 Gbps. The energy efficient design of optical transmitter and laser driver is also designed by (Abdullah etal., (2015), (Abdullah etal., (2015).
In this chapter, the authors validated the low power design using simulation and experimental results. The low power design for VLSI based system is achieved using IO Standard technique that varies the chip power during realization over UltraScale FPGA. In the next section, the basic terminologies are discussed. The basic terminologies related to this work are categorized in VLSI power consumption and its type, need of low power design in VLSI system and basic terms related to proposed technique.