Low-Power High-Performance Tunnel FET With Analysis for IoT Applications

Low-Power High-Performance Tunnel FET With Analysis for IoT Applications

Suman Lata Tripathi (Lovely Professional University, India)
DOI: 10.4018/978-1-5225-9574-8.ch002
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The emerging tunnel FET is analysed in terms of ON-state current, OFF-state current, subthreshold slope, switching capacitance to explore its applications for smaller size low-power high-speed digital and memory applications that are an integral part of portable intelligent devices for IoT applications. A large portion of IoT systems are associated with these embedded SRAM/DRAM memories that contribute to a major portion of power dissipation in systems-on-chip (SoCs) or digital design. Several SRAM cell-based memory designs with TFET structures are compared to focus their applications. The ambilpolar nature of TFET structures are investigated for highly random, unclonable secured hardware systems. New circuit designs with TFET were explored for turn-on voltage reduction, ON-state resistance reduction, and reverse leakage reduction techniques that plays an important role in designing efficient energy-harvesting systems.
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Transistor Design For Iot Systems

The significant growth in the amount of data to be processed, transmitted, and stored by IOT systems focuses the concern toward low power secured hardware structures. A low energy secured system requires new researches at different level of micro-architectures, gate level/register transfer level and transistor level design (Taheri et al, 2017). The increasing demand of Internet of Things (IoTs) as a future perspective of electronics industry requires highly energy efficient design of sensor nodes. Several IOT based applications such as sensing hazardous environmental conditions, wearable and portable health monitoring system, bio-medical sensors, remote surveillance, traffic monitoring and other sensing network require ultra-low high speed, low power and energy-efficient devices to maintain long battery life as well as embedded self energy harvesting technique (Ahmad et al, 2018). A large portion of IOT systems are associated with these embedded SRAM/DRAM memories that contribute to major portion of power dissipation in Systems-on-Chip (SoCs) or digital design (Lee et al, 2013). The flip-flops are critical components in any SoC design, so Some of literature shows flip-flop designs with FETs especially for microprocessor based systems and digital logic where flip-flops are used as pipeline registers, register files and buffers (Rasouli et al, 2006; Gupta et al, 2016). These flip-flop supports voltage scaling and works for supply voltages from 0.3V to 0.6V with improved leakage by 4 to 7 decades with advance transistor designs. The designer task is achieving secured low power micro-architectures by taking consideration for functionality, performance, power, area and overall cost. The new transistors are coming into picture with advance features to replace CMOS technology removing the scaling barriers. The technology must have some distinguished feature and performance that can be implemented for secured IOT systems with low energy. The transistors based on new technology must design by taking care for, fault models, manufacturing defects and reliability issues.

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