Machine Learning Optimization Techniques for 3D IC Physical Design

Machine Learning Optimization Techniques for 3D IC Physical Design

Gracia Nirmala Rani D. (Thiagarajar College of Engineering, India), J. Shanthi (Thiagarajar College of Engineering, India) and S. Rajaram (Thiagarajar College of Engineering, India)
DOI: 10.4018/978-1-5225-9643-1.ch003

Abstract

The importance and growth of the digital IC have become more popular because of parameters such as small feature size, high speed, low cost, less power consumption, and temperature. There have been various techniques and methodologies developed so far using different optimization algorithms and data structures based on the dimensions of the IC to improve these parameters. All these existing algorithms illustrate explicit advantages in optimizing the chip area, maximum temperature of the chip, and wire length. Though there are some advantages in these traditional algorithms, there are few demerits such as execution time, integration, and computational complexity due to the necessity of handling large number of data. Machine learning techniques produce vibrant results in such fields where it is required to handle big data in order to optimize the scaling parameters of IC design. The objective of this chapter is to give an elaborate idea of applying machine learning techniques using Bayesian theorem to create automation tool for VLSI 3D IC design steps.
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Introduction

From Transistor to Integrated Circuit technology

The invention of the first transistor in 1947 was a revolution in the field of semi- conductor technology. Several types of transistors were fabricated in the following years and they were used in variety of applications in the field of Control systems, Military, Medicine, and so on. These transistors were known to be discrete components and number of transistors was connected together on a printed circuit board (PCB) to implement different circuit functions. The planar process was developed in the year 1960, which yielded the famous technology called “Integrated Circuits” as shown in Figure.1.

Further enhancement in fabrication and integration technology yielded high density and low cost integrated circuits. Such ICs were designed and fabricated for serving a single application. Numerous logic families such as Transistor- Transistor Logic (TTL), Emitter-Coupled Logic (ECL), and Complementary Metal Oxide Semiconductor (CMOS) had been fabricated in past four decades. Later,1970s the first microprocessor was fabricated by Intel, named Microprocessor 4004,which was a four bit microprocessor capable of manipulating four bit data. From then, the microprocessors and ICs in general have consistently improved, with increase in circuit density, speed, and reliability. This evolution was foreseen by Gordon Moore as, “The Number of transistors integrated on the single chip will double in every 18 months” which is called as Moore’s Law.

Limitations of 2D Integrated Circuits

The traditional integrated circuits (ICs) also known as two-dimensional integrated circuits (2D ICs) are constructed up on the single silicon die that comprised of millions of transistors. These large numbers of devices or transistors are integrated on the single layer laterally on a planar structure. When moving to the higher end applications with a bigger circuit, the number of devices to be fabricated on the single layer is increased. If the number of devices and transistors on a single chip is increased the size of the chip, the wire-length required to connect the devices with each other are also increased. These issues predominantly affect the main advantages of the integrated circuits such as small in size, high speed. Also, since the silicon die is heavily integrated with large number of devices, the temperature of the chip is also increased due to the heat dissipation and power consumption. Increased chip size, increased wirelength and increased temperature of the chip severely affect the performance of the system.

From 2D IC to 3D IC Technology

As it is discussed earlier, there exist few limitations in 2D IC technology; a new IC technology was introduced by the researchers, called “Three Dimensional Integrated Circuits” (3D ICs). The 3D IC is designed by stacking several functional device layers vertically instead of mounting devices on a single planar structure like 2D IC and interconnection between these layers is achieved by Through Silicon Via (TSV) techniques, as shown in Figure 2. As expected, Three Dimensional Integrated Circuits (3D ICs) offer promising solutions like reduced chip area and interconnect length/wire length, while improving the electrical performance of the chip. The 3D IC with TSV is optimal finding because of the various advantages. Recently, image sensor chip, shared memory, retinal prosthesis chip, 3D SRAM has been fabricated using 3D IC technology.Some of the 3D IC examples are shown in Figure.4. Also example architecture of heterogeneous 3D SOC is represented in Figure 3.

Figure 1.

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Figure 2.
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Figure 3.
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Figure 4.

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