Memory Testing and Self-Repair

Memory Testing and Self-Repair

Mária Fischerová (Institute of Informatics of the Slovak Academy of Sciences, Slovakia) and Elena Gramatová (Institute of Informatics of the Slovak Academy of Sciences, Slovakia)
Copyright: © 2011 |Pages: 20
DOI: 10.4018/978-1-60960-212-3.ch007
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Memories are very dense structures and therefore the probability of defects is higher than in the logic and analogue blocks, which are not so densely laid out. Thus, embedded memories as the largest components of a typical SoC - up to 90% of the chip area dominate the yield of the chip. As fabrication process technology makes great progress, the total capacity of memory bits increases and will cause an extension in area investment for built-in self-testing, built-in repairing and diagnostic circuitry. Many test and repair techniques are used in industry but the research results offer new methods and algorithms for improving digital systems testing quality. The purpose of this chapter is to give a summary view of static and dynamic fault models, effective test algorithms for memory fault (defect) detection and localization, built-in self-test and classification of advanced built-in self-repair techniques supported by different types of repair allocation algorithms.
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Large and embedded memories are designed with more aggressive rules than those for the logic on the chip, so memory defect densities are typically twice that of logic. Memories are dominating blocks of nowadays and future SoCs (80-90% of a standard chip) and therefore testing and repairing them is the key point in achieving acceptable SoC yield. A post-manufacturing repair of faulty memory blocks using redundant rows and/or columns contributes to the higher SoC manufacturing quality. Redundancy involving extra rows and columns can substantially increase the memory yield. Currently, spare elements (redundant rows and columns) have become an integrated part of most embedded and commodity memories. The faulty cells can be repaired immediately after manufacturing but still unused spares can serve for replacement during the life-time of systems on chip making them more fault-tolerant. The repair process based on testing outcomes and on the repair analysis is done by external devices or by internal blocks integrated directly on chips.

In memory testing march type algorithms are mostly employed due to their linear complexity and high fault coverage. The march algorithms are scalable and flexible for different types and sizes of memories, also for various fault types, diagnosis and test application time requirements. The algorithm is composed of test elements (an element consists of writing and reading operations over memory cells) and applied by using external automatic test equipment (ATE) or a built-in self-test architecture linked to the memory. Test results obtained are an input to a repair allocation algorithm and processed after finishing the whole test or consecutively if one fault is localized. Developed repair allocation algorithms are based on analysis of a global (or local) failure bitmap created during the testing process and the spare allocation has to be done after finishing the whole memory test. The main feature of the advanced repair allocation algorithms is an ambition to find a replacement solution without using any failure bitmap that has to store too much information when the memory capacities continuously grow.

The result of any repair allocation algorithm is a relationship between addresses of the faulty memory elements and the spare elements available for repairing the diagnosed faults. Using ATE is becoming inefficient for large memories; therefore it is very important to integrate the built-in repair analysis together with a repair technique into the chip.

The built-in self-repair architectures are suitable to be designed in interleaving modes with any built-in self-test architecture. Finding an optimal solution of an ordered sequence of rows and columns by the repair analysis for large memories is NP-complete problem (Kuo & Fuchs, 1987); therefore the repair analysis is the critical challenge for built-in self-repair and then for design of fault tolerant systems on chip. The crucial parameters for finding an optimal built-in self-repair technique are the hardware overhead of chip and the test time.

According to (ITRS, 2009) the embedded memory test, repair and diagnostic logic size was up to 35 K gates per million memory bits in 2009. It contains built-in self-test, built-in redundancy analysis and built-in self-repair logic, but does not include the repair programming devices such as optical or electrical fuses.

The chapter contains a short state-of-the-art of fault models, test algorithms and current built-in self-test architectures used in memory testing. Mainly read-write memory types are used in SoCs; therefore the chapter is aimed at these memories. The main target is to present advanced built-in self-repair techniques based on two-dimensional redundancy and built-in repair-analysis algorithms suitable for fault tolerant SoCs design which use local failure bitmaps as well as those working without stored failure bitmaps.

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