Methodology for FPGA Implementation of a Chaos-Based AWGN Generator

Methodology for FPGA Implementation of a Chaos-Based AWGN Generator

Luciana De Micco (National University of Mar del Plata, Argentina) and Hilda Angela Larrondo (National University of Mar del Plata, Argentina)
DOI: 10.4018/978-1-5225-0299-9.ch003
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Abstract

Additive White Gaussian Noise (AWGN) generators are a basic tool for the test and measurement of digital systems. One drawback for hardware implementation of the classically used algorithms is that they require the hardware implementation of complex operations (such as sinusoidal and logarithmic functions). In this chapter, a method for the design and hardware implementation of an AWGN generator based on chaotic maps is described. The advantage is that deterministic chaotic systems are described by simple nonlinear equations, and therefore, they are straightforward to implement in hardware. To ensure that the generated sequence has the desired Probability Density Function (PDF), the chaotic map, which is the heart of the system, is synthesized using an approach based on the theory of positive matrices method. The hardware implementation was developed using an Altera Cyclone III FPGA with the 3C120 Development Board.
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State-Of-The-Art Awgn Implementations

In order to generate AWGN samples different methods have been developed (Papoulis & Pillai, 2001, Muller & Pauw, 1998, Tae et al., 2002, Box & Muller, 1958, Schollmeyer & Tranter, 1991, Leva, 1992, Beaulieu & Tan, 1997, Wallace, 1996, Marsaglia & Tsang, 2002, Hörmann & Leydold, 2003). Most proposed generation methods start with a temporal series of data with uniform Probability Density Function (PDF). Then applying the Box-Muller algorithm or a method based on the Central Limit theorem, time series with Gaussian PDF is obtained (Thomas et al., 2009, Thomas et al., 2007). Unfortunately, in practice the Central Limit theorem requires an impractically large number of samples to achieve an accurate representation of the ideal Gaussian PDF.

The rejection-acceptance methods (Leva, 1992, Marsaglia & Tsang, 2002, Ahrens & Dieter, 1989, Knuth, 1997, Leydold, 2000) are mainly used in software implementations, in the case of this chapter, where a hardware implementation is the objective, they are not useful because the output rates are not constant, this is due to the conditional loops that the algorithms have.

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