Co-Modeling of Embedded Networks Using SystemC and SDL

Embedded Systems Design Flow

An embedded system is a combination of computer hardware and software (could have fixed capability or be programmable) that is specifically designed for a particular function. This makes it a system dedicated for an application(s), its specific parts or parts of a larger system. An embedded system is built to control a function or range of functions and usually have strict real-time computational restrictions (Heath, 2003; Barr & Massa, 2006; Kamal, 2008).

Embedded systems span all aspects of modern life and there are many examples of their use. They are cash dispenses, payment terminals, handheld computers, mobile phones, telecommunication equipment and so on.

Many different activities are required to carry a complex electronic system from initial idea to the physical implementation. Performance modeling helps to understand and establish the major functional and nonfunctional characteristics of the product. Functional modeling results in a specification of the functional behavior of the product. Design and synthesis refine the product specification into a sequence of design descriptions that contain progressively more design decisions and implementation details. Validation and verification hopefully ensure that the final implementation behaves as specified. All these activities operate on models and not on the real physical object. One obvious reason for using a model is that the real product is not available before the development task is completed (Jantsch, 2004).

But the embedded systems design encounters a number of difficulties caused by increasing complexity of projects, increasing requirements to products reliability, power consumption and demand to speed-up the project design phase. The modern approach to the system design is illustrated by Figure 1 and includes the following stages:

Figure 1.

General design flow

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  Conceptual System Design: The primary goal of this stage is the formulation of the main system design choice, analysis of the system design and development of the specification draft;

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  Specification: This stage is targeted to get the final version of the system specification and benefits from having the model done in a high-level language, usually in С/С ++, SystemC, SDL;

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  Logical Design: Converting the executable project specification to the register transfer level, i.e., the result is a specification implementation in Verilog/VHDL and further at the gate level. In this context can be also called – architectural design;

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  Project Verification: Verification of the design decisions in conformity to the specification and other requirements, in the course of design and detailed elaboration process;

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  Physical Design: This stage begins from the selection of technological and library basis, and it is completed when there is the final specification of the project in GDSII format. GDSII is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form.