A Novel DCGA Optimization Technique for Guaranteed BIBO-Stable Frequency-Response Masking Digital Filters Incorporating Bilinear Lossless Discrete-integrator IIR Interpolation Sub-Filters

A Novel DCGA Optimization Technique for Guaranteed BIBO-Stable Frequency-Response Masking Digital Filters Incorporating Bilinear Lossless Discrete-integrator IIR Interpolation Sub-Filters

Syed Bokhari (University of Alberta, Canada) and Behrouz Nowrouzian (University of Alberta, Canada)
DOI: 10.4018/978-1-60960-018-1.ch014

Abstract

This work is concerned with the development of a novel diversity-controlled (DC) genetic algorithm (GA) for the design and rapid optimization of frequency-response masking (FRM) digital filters incorporating bilinear lossless discrete-integrator (LDI) IIR interpolation sub-filters. The selection of FRM approach is inspired by the fact it lends itself to the design of practical sharp-transition band digital filters in terms of gradual-transition band FIR interpolation sub-filters. The proposed DCGA optimization is carried out over the canonical-signed-digit (CSD) multiplier coefficient space, resulting in FRM digital filters which are capable of direct implementation in digital hardware. A novel CSD look-up table (LUT) scheme is developed so that in every stage of DCGA optimization, the IIR interpolation sub-filters constituent in the intermediate and final FRM digital filters are guaranteed to be automatically BIBO stable. The proposed DCGA optimization permits simultaneous optimization of the magnitude-frequency as well of the group-delay frequency response of the desired FRM digital filters. An example is given to illustrate the application of the resulting DCGA optimization to the design of a lowpass FRM digital filter incorporating a fifth-order bilinear-LDI interpolation subfilter.
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Introduction

In many practical situations in the design and implementation of circuits and systems on hardware platforms, it is required for the resulting piece of hardware to be capable of adapting to changing environments. The main motivation behind this adaptability is to improve the performance characteristics of the resulting hardware implementation, and to prolong its operational lifetime. The notion of Evolvable Hardware (EH) has been developed to refer to a hardware piece that can change not only its performance parameters but also its configuration dynamically and autonomously by interacting with its environment. This is achieved through the use of reconfigurable hardware (e.g. programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) on the one hand, and artificial intelligence computations (including evolutionary algorithms (EAs) and artificial neural networks (ANNs) on the other (Stoica, 2000).

The autonomous reconfigurabilty feature of EH makes it fundamentally different from conventional hardware, where the architecture and function of the hardware remain fixed past its implementation. Moreover, while programmable hardware devices like FPGAs allow for limited functional changes after implementation, such changes can only take place by human intervention. With the use of EAs and ANNs, however, EH is capable of autonomously changing its configuration and function, providing an attractive approach to making the hardware “soft” by adapting it to its environment dynamically (Higuchi, Liu, & Yao, 2006).

In principle, EH can be considered as a combination of hardware and its control subsystem, where the purpose of the control subsystem is to set the configuration and function of the hardware proper dynamically based on the environment. This is usually the case when the corresponding control subsystem has been developed and refined to the extent that it can co-exist with the hardware on the same platform for online operation. Otherwise, i.e. in offline applications, the control subsystem resides separately from the hardware proper, usually in the form of a computational engine. Of course, once the operation of the computational engine has been streamlined adequately, it can be incorporated as a part and parcel of the actual EH.

This work is concerned with the development of a control subsystem for a class of EH frequency-response masking (FRM) digital filters by employing an EA, where the EA is applied to the optimization of the values of the FRM digital multiplier coefficients based on given a set of target design specifications. Such an optimization turns out to have a multi-modal cost function, and requires built-in internal or external mechanisms for escaping from local optimal solutions during the course of optimization.

Genetic Algorithms (GAs), (Goldberg, 1989) are optimization techniques which simulate natural selection and reproduction to move towards an optimal solution, and closely resemble the concept of biological evolution. It is well known that GAs provide a promising approach to solve discrete and multimodal optimization problems due to the fact that they are capable of automatically finding near-optimal solutions while keeping the computational complexity of the optimization at moderate levels. Consequently, they have emerged as an attractive alternative for the optimization of FIR as well as IIR digital filters. These algorithms encode the digital filter design variables into a chromosome (usually as a binary string), and proceed towards an optimal solution through the evolution of a population of potential candidate chromosomes in an iterative manner from one generation to the next.

Unfortunately, the conventional GAs do not search the solution space robustly due to lack of mechanisms through which entrapment at local optimal solutions can be avoided. It was demonstrated by Shimodaira in (Shimodaira, 2001) that diversity control (DC) can be exploited to help to increase the convergence speed of conventional GAs. The main principle behind DCGA is to increase the diversity of the population pool through the incorporation of additional non-elite chromosomes based on a pair of external control parameters.

In principle, DCGA is capable of finding the global optimal solution provided that no bound is imposed on the constituent number of generations. However, in practical situations, DCGA is set to terminate once all of the design specifications have been satisfied. In such situations, the resulting solution may or may not represent the global optimal solution, but simply a solution that satisfies all of the given target design specifications.

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