On-Chip Networks for Modern Large-Scale Chips

On-Chip Networks for Modern Large-Scale Chips

George Michelogiannakis (Lawrence Berkeley National Laboratory, USA)
Copyright: © 2015 |Pages: 10
DOI: 10.4018/978-1-4666-5888-2.ch616
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Background

On-chip networks are composed of a set of routers interconnected by point-to-point links. The manner routers are connected to each other and thus the layout of the network is specified by the topology. While numerous topologies have been proposed, the most widely used topology is the 2D mesh due to its simplicity and modularity. In the 2D mesh, each router is connected only to its neighbors. Each router is also connected with a local processing, cache or other block through a network interface. In a N-by-N 2D mesh the average number of hops is approximately while the maximum number of hops is . A 3x3 2D mesh is shown in Figure 1.

Figure 1.

In a 2D mesh each router is connected only to its neighbors

Key Terms in this Chapter

Arbiter: A logic block which receives N requests and grants one with some criteria.

Zero-load latency: The latency from the source to the destination in the absence of contention.

Cache: A fast storage block that is placed close to processing cores but is much smaller than the system memory. It contains frequently-accessed variables for fast access.

Parallel Computing: The discipline about programming and designing systems to use multiple processing cores for a single application.

Flow Control: The mechanism which guarantees correct propagation of packets through the network. Flow control can provide more functionality, such as separation between traffic classes.

Hop: A channel traversal, including injection and ejection channels.

Livelock: A situation where packet movement exists in the network, but that does not constitute forward progress. For example, packets moving in circles for infinity constitute a livelock situation.

Execution Thread: A part of a program that can execute in parallel with other execution threads.

First In First Out (FIFO): A data structure where the first entry to enter is the first entry to depart.

Saturation: A state at which the network cannot accept offered traffic and therefore buffer occupancy at the injection points constantly increases.

Cache Coherency: The protocol that ensures that copies of data in a shared address space stored in local processor caches are consistent (up to date). This includes searching for and invalidating data in remote caches.

Uniprocessor: A system with a single processing core.

Superscalar: Processors that can issue and commit multiple instructions per cycle.

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