# Optimal Placement of Power Factor Correction Capacitors Using Taguchi Optimization Method

Abdelmadjid Recioui (University of Boumerdes, Algeria)
DOI: 10.4018/978-1-5225-2990-3.ch033

## Abstract

This chapter presents two methods to optimize the placement of capacitors in a distribution system and thus correcting power factor and reducing losses and costs. The first method uses ETAP software and its integrated algorithm of optimally placing power factor correction capacitors. The second uses the Taguchi Optimization method to solve the optimal capacitor placement problem in electric distribution systems. To test the efficiency of these methods, they were applied to various examples (different bus systems) and simulation results of the two methods are discussed.
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## Motivation

Capacitor placement in distribution systems helps improve power factor, bus voltage regulation, reduce power and energy loss, increase system capacity in addition to enhancing the power quality (Riese, 2012).

There exist two main strategies to deal with the problem of capacitor placement for reactive power compensation. Either one would place a bank of capacitors at each power system bus or placing a bank of capacitors at the mains to enhance the overall power factor. The effectiveness of either strategy depends on the criticality of the power factor deterioration problem. Indeed, the first strategy is not economically sound but allows the control of the individual reactive powers at each bus. The second strategy is cheap but no control on the individual bus reactive power levels is possible.

To compromise between the two philosophies, one would ask how capacitors are placed and controlled under some loading conditions. This means that the capacitor placement problem turns to an optimization problem and it should be formulated with the desired objective function (such as loss minimization) and various technical constraints (e.g. the limits of voltage levels and power flow) (Riese, 2012). The proper solution techniques should be applied to simultaneously determine the optimal number, location, type, size and control settings at different load levels of the capacitors to be installed (Eaton, 2014; Tagare, 2000). Because capacitor sizes and locations are discrete variables, the capacitor placement problem has a combinatorial nature. The problem is a binary decision making problem with discrete steps of standard bank size of capacitors.

Thanks to the rapid development of computer technology, many optimization techniques such as genetic algorithm (GA), particle swarm optimization (PSO), simulated annealing (SA), artificial neural network (ANN), and gradient-based techniques have been implemented in the form of computer codes (Weng et al., 2007). These global optimizers while more familiar, traditional techniques such as conjugate gradient and the quasi-Newtonian methods are classified as local optimizers. The distinction between local and global search of optimization techniques is that the local techniques produce results that are highly dependent on the starting point or initial guess, while the global methods are highly independent of the initial conditions (Recioui, 2012). Though they possess the characteristic of being fast in convergence, local techniques, in particular the quasi-Newtonian techniques have a direct dependence on the existence of at least the first derivative. In addition, they place constraints on the solution space such as differentiability and continuity, conditions that are hard or even impossible to deal with in practice (Recioui, 2012). Compared to the traditional optimization techniques, Taguchi’s optimization method is easy to implement and very efficient in reaching optimum solutions. Taguchi’s optimization method is developed based on the orthogonal array (OA) concept, which offers a systematic and efficient way to select design parameters. In addition, it reduces the number of tests required in the optimization process compared to GA or PSO (Weng et al., 2007).

In this chapter, Taguchi method is applied to the optimal placement of power factor correction capacitors with the objective to improve power factor and reduce the cost of energy losses. Various examples (different bus systems) and simulation results of the applied technique are shown and discussed.

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