Optimization of CMOS Quadrature VCO Using a Graphical Method

Optimization of CMOS Quadrature VCO Using a Graphical Method

Hassene Mnif, Dorra Mellouli, Mourad Loulou
Copyright: © 2012 |Pages: 15
DOI: 10.4018/978-1-60566-886-4.ch005
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Abstract

This chapter describes the design and the optimization of Quadrature Voltage Controlled Oscillators (QVCOs) based on the coupling of two LC-tank VCO. This work covers the phase noise analysis, a graphical optimization approach, already used to optimize LC oscillator phase noise (Andreani, Bonfanti, Romano, & Samori, 2002), to optimize QVCO phase noise while satisfying design constraints such as power dissipation, tank amplitude, tuning range and start up condition. The cross-coupling transistors impact on phase noise for different configurations is especially addressed. The obtained BS-QVCO, using 0.35µm CMOS process, can be tuned between 2.2GHz and 2.58GHz, and shows a phase noise of -129 dBc/Hz at 1MHz offset from a 2.4 GHz carrier, for a current consumption of 9.25mW. The equivalent phase error and amplitude error between I and Q signals are respectively 0.65° and 1.87%.
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Quadrature Oscillators

In low-IF or Zero-IF transceivers, quadrature signals (0° and 90°) are needed for I/Q (modulation / demodulation). It is important to offer quadrature generation at a minimal phase noise and power consumption. A way for obtaining quadrature signals is through the use of a VCO design enabling to deliver such signals. In principal, a ring oscillator fulfills this requirement, however its notorious high phase noise disqualifies this choice for most application in modern radio transceivers (Andreani & Bonfanti, 2002). A more attractive approach to direct quadrature synthesis relies on the possibility of coupling two symmetric LC-tank VCOs to each other, thereby exploiting the good phase performance of LC-oscillator (Tiebout, 2001, pp. 1018-1024). As exemplified by the block schematic in Figure 1, the combination of a direct connection and a cross connection forces the two VCOs to oscillate in quadrature.

Figure 1.

Block schematic and signal phases for a QVCO

978-1-60566-886-4.ch005.f01

The original QVCO based on the cross-coupling transistors Mcpl placed in parallel with the switch transistors Msw (Rofougaran & Rael, 1996, pp.135-136) (Figure 2-a), was known to have a poor phase-noise behavior. This QVCO design will be referred as the parallel QVCO (P-QVCO). To improve overall performance we will place Mcpl in series with Msw, rather than in parallel (Figure 2-b). This choice is motivated by the fact that Mcpl in the P-QVCO is responsible for a large contribution to the phase noise, and placing Mcpl in series with Msw, should greatly reduce the noise from the cascade device. Since, in this case Mcpl is placed at the bottom of Msw. This is the bottom series QVCO (BS-QVCO).

Figure 2.

Conventional QVCO schematic: (a) P-QVCO; (b) BS-QVCO

978-1-60566-886-4.ch005.f02

The architecture of each LC-VCO is a cross-coupled structure with NMOS and PMOS transistors. The inductance-capacitance (LC) resonant circuit comprises an inductor and a differentially tuned varactor. The tail current source is a simple NMOS current mirror. The resonant circuit and the cross-coupled complementary N-PMOS pair are fully differential to reduce the sensitivity to power supply variations and substrate interferences and noise.

The oscillation frequency f0 is controlled by the LC-tank and can be expressed by:

978-1-60566-886-4.ch005.m01
(1)

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