Performance and Complexity Evaluation of OTR-UWB Receiver

Performance and Complexity Evaluation of OTR-UWB Receiver

Hossein Gharaee (Tarbiat Modares University, Iran), Abdolreza Nabavi (Tarbiat Modares University, Iran) and Jalil ("Joe") Etminan (Rock Valley College, USA)
DOI: 10.4018/978-1-60566-986-1.ch123
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This article presents a new transmitted reference UWB receiver, which utilizes the orthogonal property of even and odd order derivatives of Gaussian pulses in neighboring chips for synchronization. This system, referred to as orthogonal TR-UWB (OTR-UWB), employs only a single spreading code, which results in much lower mean detection time compared to DS-UWB systems. The hardware complexity for OTR-UWB receiver is significantly reduced against conventional TR-UWB systems. In addition, simulation results show that BER performance is improved, while the new system is capable of supporting higher data rates. Also, this article presents the FPGA implementation of OTR-UWB, with a bit-rate of 25Mb/s without using equalizer. In addition, we present the DSP algorithm of baseband. Hardware of this system is implemented on two different FPGAs from ALTERA and XILINX, CycloneII (EP2C35F672C6) and Spartan 3 (3s4000fg676-5). Gate estimation and power analysis are performed by Quartus II 7.2 (ALTERA) and ISE 8.1 (XILINX) softwares.

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