Power Optimization Using Clock Gating and Power Gating: A Review

Power Optimization Using Clock Gating and Power Gating: A Review

Arsalan Shahid (HITEC University, Pakistan), Saad Arif (HITEC University, Pakistan), Muhammad Yasir Qadri (University of Essex, UK) and Saba Munawar (COMSATS Institute of Information Technology, Pakistan)
DOI: 10.4018/978-1-5225-0287-6.ch001
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Abstract

The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components level are proposed by the research community such as clock gating, operand isolation, memory splitting, power gating, dynamic voltage and frequency scaling, etc. This chapter reviews advancements in the dynamic power optimization techniques like clock gating and power gating. This chapter also reviews some architectures and optimization techniques that have been developed for greater power reduction without any significant performance degradation or area cost.
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Background

Reducing the power consumption has become one of very important research interest and a great challenge in various computing platform for the past decade. In this section we will discuss various techniques used for power optimization. Moreover, we will discuss the advantages of power gating and clock gating techniques over the other available techniques.

Power dissipation has emerged as an important factor in the design phase of a microprocessor. Careful and intelligent design is required at different levels of computer system to obtain optimal power performance. Therefore, it is very important to know the sources of energy consumption at different levels of memory hierarchies. Various energy models have been presented to understand the accurate power consumptions by integration with different cycle accurate simulators. One such example is energy models of multilevel cache memory presented by Qadri et al. (Qadri, M. Y., & McDonald-Maier, K. D., 2010). Energy models can also be subdivided in to three types, i.e., CPU level Energy models (Brooks, D. M. et al, 2000), complete system level models and interconnect level energy models. Hence, energy models do provide a very deep level of energy consumption analysis and result in to power optimization. Then comes the Dynamic Power Measurement (DPM) techniques, which can be classified into three subcategories:

  • 1.

    CPU level DPM,

  • 2.

    Complete system level DPM, and

  • 3.

    Parallel system-level DPM.

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