Reliability and Security Challenges in Electrical/Optical On-Chip Interconnects for IoT Applications

Reliability and Security Challenges in Electrical/Optical On-Chip Interconnects for IoT Applications

Muhammad Rehan Yahya (Nanjing University of Aeronautics and Astronautics, China), Ning Wu (Nanjing University of Aeronautics and Astronautics, China) and Zain Anwar Ali (Sir Syed University of Engineering and Technology (SSUET), Pakistan)
DOI: 10.4018/978-1-7998-1253-1.ch011

Abstract

The evolution of internet of things (IoT) applications, cloud computing, smart cities, and 4G/5G wireless communication systems have significantly increased the demands for on chip processing. Network on chip (NoC) is a viable alternative that can provide higher processing and bandwidth for increasing demands. NoC offers better performance and more flexibility with lower communication latency and higher throughput. However, use of NoC-based IoT devices have raised concerns on security and reliability of integrated chips (IC), which is used in almost every application. IoT devices share data that becomes vulnerable to attack and can be compromised during the data transfer. Keeping in view these security challenges, a detailed survey is presented that covers the security issues and challenges focusing on NoCs along with proposed countermeasures to secure on-chip communication. This study includes on-chip security issues for electrical as well as optical on-chip interconnects.
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Introduction

The evolution of internet of things (IoT) inspires smart devices that are permeating in our lives, where smart services and applications are performing critical tasks that raise security concerns. Data proliferation is one of the critical issues, which designers and researchers are facing with the advent of IoT based smart cities projects (Samaila, Neto, Fernandes, Freire, & Inácio, 2018). With the increase in processing demand for IoT applications in every day of life, security and dependability have become key concerns while designing a network on chip based CMPs. Intellectual property (IP) hardware from third-parties are frequently used in order to reduce design time. The use of these IPs could cause leakage of data/information due to presence of some malicious Hardware Trojan (HT) (Basak, Bhunia, Tkacik, & Ray, 2017), (Tehranipoor & Koushanfar, 2010). The reason for information leakage may be unverified IPs, malicious foundry or untrusted design procedure. This problem of security lead researchers and designers to focus on security and reliability issues of on-chip interconnects (Bhunia et al., 2013). Network on Chip (NoC) has evolved as a practical solution that can provide future interconnection and processing requirements for IoT applications in chip multiprocessors (CMPs) (Bertozzi, Dimitrakopoulos, Flich, & Sonntag, 2015). In past, few works have been proposed to discuss security challenges in NoC based systems (Ben Achballah, Ben Othman, & Ben Saoud, 2017). However, more research needs to be accomplished for both electrical and optical NoC domains for secure on-chip communication. Figure 1 shows the IoT system setup with smart applications and services (Samaila et al., 2018).

Figure 1.

Smart City Concept based on IoT System including smart applications of mobility, health and daily life

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As technology has exponentially evolved over the last few years, the number of cores on a single die has increased at a rapid pace, especially during the last decade. In this regard, the trend of technological developments in terms of increase in per chip core count, the increase in number of transistors, escalation in frequency and power consumption has been presented in form of trending plot titled “35 Years of Microprocessor Trend Data”, which has been initially presented by M. Horowitz et. al till 2010 (M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond, and C. Batten, 2018). Later, the plots have been updated by K. Rupp from 2010-2017. It can be observed from the Figure 2 that the number of per chip cores is increasing with a power law. Since the number of transistors is increasing as per Moore's Law, therefore chip count is increasing in form on-chip additional cores.

Figure 2.

Original data up to the year 2010 collected and plotted by M. Horowitz, F. Labonte, O. Shacham, K. Olukotun, L. Hammond, and C. Batten. New plot and data collected for 2010-2017 by K.Rupp

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