Risks Analysis and Mitigation Technique in EDA Sector: VLSI Supply Chain

Design Capture Tools

This is the first and most important category of EDA tools since it deals with the designer’s specifications. By capturing here means abstracting and encapsulating a circuit description and preparing the same for further simulations as per SAE (simulation and analysis environment). Collectively, the work at this entry level can be shown by Figure 1.

Figure 1.

Operations performed by Design capture tools

Simulation Tools

The next set of tools that deal with Front-end IC design. Again these are further classified on the basis of operations performed. One type is for the functional verification of the design, and second one verifying the timing specifications, viz. STA tools, Power analyzers etc. The former one verifies the logic behavior of the IC design corresponding to entry level specification (i.e. in reference to gate level net-list). One must take care to characterize all the design primitives during formal simulation. Later tools make sure that timing constraints viz. set-up and hold time are met accordingly in proper synchronized way (Mead C. et al, 2012).

The timing simulation is performed on multiple level of abstraction so definitely it is required to be done in a careful and efficient manner. The information thus retrieved by these tools is then back-annotated for final logic simulations after the floor planning and layout of the design.

Layout Tools

These are the tool that performs the design tasks just before the actual implementation of the design for verifying inter-connects, technology parameters, floor plan, clock and data paths etc. They allows transforming the logic implementation to a physical design laying a path towards ASIC (Application specific IC) design (Zimmermann, R. et al., 1999). Now here comes the categorization based upon customization process, viz. semi and full custom design. In later the customization deals from designing a cell level ASIC representation and then combing those to form sub-components and finally having the complete design. The former one requires getting Intellectual properties from different EDA vendors and hence combining those components and verifying as a design. The physical design tools always works in conjunction with the floor planning tools showing the verified cells to go on an ASIC die (Taur, Y. et al., 2013).

Synthesis and Optimization Tools

The synthesis tools will now take on functionality descriptions from HDL tools and gate level net-lists and then mapping them with the placement and routing (layout) tools. The mapping is done targeting a specific library in a technology specific manner to obtain area, power and delay optimization.