A Road Map for the Validation, Verification and Testing of Discrete Event Simulation

A Road Map for the Validation, Verification and Testing of Discrete Event Simulation

Evon M. O. Abu-Taieh (The Arab Academy for Banking and Financial Sciences, Jordan) and Asim Abdel Rahman El Sheikh (The Arab Academy for Banking and Financial Sciences, Jordan)
DOI: 10.4018/978-1-60566-026-4.ch526
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Abstract

The aim of this chapter is to give an elaborate reasoning for the motivation for Validation, Verification, and Testing (VV&T) in Simulation. Thereby, defining Simulation in its broadest aspect as embodying a certain model to represent the behavior of a system, whether that may be an economic or an engineering one, with which conducting experiments is attainable. Such a technique enables the management, when studying models currently used, to take appropriate measures and make fitting decisions that would further complement today’s growth sustainability efforts, apart from cost decrease, as well as service delivery assurance. As such, the Computer Simulation technique contributed in cost decline; depicting the “cause and effect,” pinpointing task-oriented needs or service delivery assurance, exploring possible alternatives, identifying problems, as well as proposing streamlined, measurable, deliverable, solutions, providing the platform for change strategy introduction, introducing potential prudent investment opportunities, and finally, providing a safety net when conducting training courses. Yet, the simulation development process is hindered due to many reasons. Like a rose, Computer Simulation technique, does not exist without thorns, of which the length, as well as the communication during the development life cycle. Simulation reflects real-life problems; hence, it addresses numerous scenarios with handful of variables. Not only is it costly, as well as liable for human judgment, but also, the results are complicated and can be misinterpreted.
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Background

There are four characteristics, which distinguish simulation from any other software intensive work, that also makes distinction VV&T for simulation from VV& T for other software. The four characteristics were discussed by Page and Nance (1997): time, correctness, computational intensive, and the uses of simulation. In simulation there is an indexing variable, called TIME, that “establishes an ordering of behavioral events” (p. 91). The objective of correctness is very special to simulation software for this simple reason: how useful is simulation program “if questions remain concerning its validity” (p.91). Simulation is computational intensiveness; therefore, the execution efficiency is essential due to the repetitive sample generation for statistical analysis and testing alternatives. Uses of simulation: the uses of simulation are not typical; in fact there is “No typical use for simulation can be described” (p.91).

Accordingly, validation and verification methods and techniques that relate to simulation have been thoroughly discussed by 137 research papers in the Winter Simulation Conference (WSC) over the years 1997 through 2006, as seen in Table 1 and Figure 1, highlighting the fact that such numbers clearly indicate the importance, inimitable, and unique case of validation, verification, and testing of simulation software.

Table 1.
Published research of V & V in WSC adapted from (Abu-Taieh & ElSheikh, 2006)
YearV & V PapersTotal Published PapersPercentage
1997152805%
1998222369%
19992624411%
2000192807%
2001152247%
200211191%
2003122635%
200462802%
2005114123%
2006104122%
Total13727505%
Average13.72755%

Key Terms in this Chapter

Formal VV&T Techniques: Based on mathematical proof, stating that “Current state-of-the-art formal proof of correctness techniques are simply not capable of being applied to even a reasonably complex simulation model” ( Balci, 1994 , p. 218).

Adaptive Techniques: Refers to VV&T techniques that were adapted to object-oriented theory.

Constraint VV&T Techniques: Employed to assess model correctness using assertion checking, boundary analysis, and inductive assertions.” ( Balci, 1994 , p. 218).

Verification: Answering the question, “Are we building the product right?”.

Symbolic VV&T Techniques: Techniques that uses graphical or symbols to represent the VV&T process and to simplify it.

Informal VV&T Technique: Includes tools and approaches that “relay heavily on human reasoning” ( Balci, 1994 , p.217) rather than “mathematical formalism” ( Balci, 1994 , p.217).

Specific Techniques: Which are newly created based on object-oriented formalism and used for object –oriented software.

Static VV&T Techniques: Concentrate on the source code of the model and need not the execution of the code ( Hoffer et al., 2005 ), more importantly, Balci has stated that automated tools and the language compilers relay on this type of VV&T ( Balci, 1994 ).

Dynamic VV&T Techniques: Distinguishing characteristic is for the model execution in order to evaluate the model as Balci (1994) states.

Simulation: “Is the imitation of the operation of a real-world process or system over time” (Banks, 1999 AU16: The in-text citation "Banks, 1999" is not in the reference list. Please correct the citation, add the reference to the list, or delete the citation. ).

Validation: Raising the question “are we building the right product?”.

Conventional Techniques: Refer mainly to VV&T techniques used in the object-oriented simulation without any adaptation to OOP.

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