Scalable Architecture for Heterogeneous Environment

Scalable Architecture for Heterogeneous Environment

DOI: 10.4018/978-1-4666-7312-0.ch012
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Along with the heterogeneous devices, Web-based content increases the necessity for computational services. However, recent trends make it difficult to execute such computations at the terminal side, whereas service providers often allow computations during different load operations. Many computational services are using conventional distributed systems, which provide successful packet transmission in IP networks. In this chapter, proxy architecture and its related tasks are discussed. Some of the necessary requirements, such as incremental scalability, 24x7 availability, and cost-effectiveness, are recognized for scalable network services. To administrate a large cluster and to construct a cluster-based scalable network services, a layered architecture is recommended. This architecture captures the scalable network service requirements and utilizes service-programming models to perform Transformation, Aggregation, Caching, and Customization (TACC) of Internet substance. For better performance, the architecture with the TACC programming model uses data semantics to create novel network services.
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Different types of environments like multiple radio access technologies, architectures, base stations with altering transmission power are involved in the heterogeneous mobile network environment. The swift growth of mobile computing with mixed range of technologies affects both the devices and the systems in the mobile computing domain.

The systems that employ various types of computational units like General Purpose Processor (GPP), special purpose processor, co-processor or custom acceleration logic are known as heterogeneous computing systems. Digital Signal Processor (DSP) or Graphics Processing Unit (GPU) can be used as special purpose processor and Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) can be used as custom acceleration logic (Pandey, & Glesner, 2006).

In general, various processors with diverse Instruction Set Architectures (ISAs) are constituted in heterogeneous computing platform. The requirement of high performance and spontaneous systems that can communicate with other environments had increased the demand of heterogeneous computing systems. The performance of most of the computer applications is increased without making any modifications in the structure or traditional hardware and was possible with enormous advancement in the technology and frequency scaling. Specialized resources which make the computing system to be heterogeneous are launched in addition to the primary method to gain an extra performance. There is a possibility for the designer to select different processing elements based on the tasks that a system need to perform in the case of heterogeneous computing systems. These heterogeneous systems are also referred as parallel computing systems or multi-core systems or hybrid computing because they incorporate independent computing resources and asymmetric computational units. As the area of the chip increases and the technology of fabrication are enhanced, it is possible to integrate more number of discrete components on chip, hence increases the level of heterogeneity in the modern computing systems. For instance presently, the logic for interfacing the devices with the processor (SATA, PCI, Ethernet, RFID, Radios, UARTs, and memory controllers), programmable functional units and hardware accelerators (GPUs, cryptography co-processors, programmable network processors, A/V encoders/decoders, etc.) are built-in in most of the new processors.

Many new challenges are imposed by the heterogeneous computing systems when compared to the homogeneous systems. The problems related to the homogeneous parallel processing systems are also included heterogeneous systems because it includes multiple processing components. At the same time, non-uniformity is introduced in the development of the system, practices of programming and the complete system capability.

Areas of heterogeneity (Chawathe, Fink, McCanne, & Brewer, 1998) can include:

  • ISA or Instruction Set Architecture: Two-fold incompatibility arises because of the different instruction set architectures for different computing elements.

  • ABI or Application Binary Interface: Memory is interpreted in various ways by different computing elements. The interpretation may be based on the convention, memory layout, architecture and the compiler being used.

  • API or Application Programming Interface: All the computing elements may not be uniformly obtaining a chance for the library and OS services.

  • Low-level Implementation of Language Features: In heterogeneous environments, additional translation or abstraction is required in the case of function pointers, which are used to implement the language features like functions and threads.

  • Memory Interface and Hierarchy: Cache structures, cache coherency protocols might be different for different computing elements. Similarly, the memory access might be uniform or non-uniform and the arbitrary data length that a processor can read at a time might be byte, word or burst access.

  • Interconnect: Besides basic memory/bus interfaces, different computing elements might have different types of interfaces like dedicated network interfaces, direct memory access (DMA), mailboxes, FIFOs, scratchpad memories, etc.

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