Self-Repair Technology for Global Interconnects on SoCs

Introduction

The total wire length on a chip will increase continuously (International Technology Roadmap for Semiconductors Interconnect, 2007). Simultaneously, the wire pitch and diameter will shrink, while the aspect ratio will increase. The current density will grow, because the voltage cannot be reduced on a linear scale with the wire diameter. Hence the RC delay will increase. These trends have a negative impact on the chip and system reliability. A longer wire has a higher probability to fail than a shorter one under the assumption that all other parameters are equal. The same is true for the number of wires. The decreased wire pitch makes fabrication more difficult. Faults are more likely. While defects introduced at the time of production are one reason, defects that may occur due to wear-out effects, seem to gain importance with shrinking feature size. Two of the most important wear-out effects are electro and stress migration. A high current density under higher temperature or mechanical stress between metal and silicon can lead to a transport of metal atoms. This transport leads to voids and hillocks, which can end up in a open wire or shorts because of broken insulators. The increasing aspect ratio leads to larger capacitances between adjacent wires. Coupling capacitances between lines lead to statistical variations in signal delays, which can end up in dynamic faults. The voltage drops on supply lines make the circuit more prone to transient faults, caused by the voltage supply noise or electro-magnetic interferences.

The impact of the reliability of the integrated interconnects on the overall system reliability is increasing. Global interconnects play an important role in system-on-chip (SoC). They are used to connect different cores and for test access mechanisms (TAM) (Zorian & Marinissen, 2000). The test access mechanisms are needed to transport test vectors and answers to and from the embedded cores. Fault tolerant TAM is necessary to test integrated cores and to isolate them in case of an error which could be caused by defects on local interconnects. The same is true for interconnects used for global communication. With fault tolerant global communication and test access mechanisms, graceful degradation is possible.

In this chapter, we will show what is done and what can be further done to ensure a high level of reliability also under economic aspects. Several established methods to increase the reliability are to be shown first, followed by new methods and architectures. In the following background section, we will introduce the existing and upcoming types of faults and fault mechanisms. Later we will show how they can be prevented, and if necessary, corrected using codes or built-in self repair. The next section – Built-in self-repair (BISR) of interconnects – is the main section of this chapter. At the beginning of this section, we define the goals the solutions have to meet. Then we explore the design space to see which solutions are possible. This allows us to develop the system level. To keep it vivid, we describe two examples, which will be implemented down to the register transfer level. This is necessary to obtain values for the reliability model to show the benefit of the additional circuits. Subsequent to this section, we present possible research directions, followed by the conclusions and references.