Sequential Test Set Compaction in LFSR Reseeding

Sequential Test Set Compaction in LFSR Reseeding

Artur Jutman (Tallinn University of Technology, Estonia), Igor Aleksejev (Tallinn University of Technology, Estonia) and Jaan Raik (Tallinn University of Technology, Estonia)
Copyright: © 2011 |Pages: 18
DOI: 10.4018/978-1-60960-212-3.ch022
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Abstract

This chapter further details the topic of embedded self-test directing the reader towards the aspects of embedded test generation and test sequence optimization. The authors will brief the basics of widely used pseudorandom test generators and consider different techniques targeting the optimization of fault coverage characteristics of generated sequences. The authors will make the main focus on one optimization technique that is applicable to reseeding-based test generators and that uses a test compaction methodology. The technique exploits a great similarity in the way the faults are covered by pseudorandom sequences and by patterns generated for sequential designs. Hence, the test compaction methodology previously developed for the latter problem can be successfully reused in embedded testing.
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Introduction

Accordingly to International Technology Roadmap for Semiconductors (ITRS, 2009) the last decade was a period of continuous transition when testing of complex nanoscale semiconductor devices faced a strong shift from classical methodologies towards self-test, self-diagnosis, and self-repair solutions – all to improve manufacturability and reliability characteristics of the final product. Such trend will be valid in the years to come as the design paradigm is continuously moving towards complex systems-on-chip (SOC), hence making it difficult to drive huge volumes of test data in and out of the devices under test (DUT). The latter aspect is detailed in Chapter 51 and Chapter 52 of the current book.

Due to providing a measurable structural fault coverage metric while being implemented deep down at the system’s component level and being able to work autonomously at DUT’s operating speed, Built-In Self-Test (BIST) becomes a necessary element of modern high performance and mission critical embedded systems and integrated circuits (IC). By utilizing BIST and built-in diagnosis techniques it is possible to keep production costs at reasonable levels when moving to finer and less reliable manufacturing technologies. The same techniques are often reused later in the product’s life cycle to check and diagnose the system in the field. BIST is often a part of fault management system used in fault tolerant devices (in this book see e.g. Chapter 10 and Chapter 16).

Traditional structural testing approaches based on external automated test equipment (ATE) use pre-calculated test data, generated by model-based automated test pattern generators (ATPG). In most cases, the ATPG tests are very efficient in terms of fault coverage and test size (Figure 1, ATPG curve). However, in embedded testing all such patterns need to be stored in the internal memory, which makes such a solution quite a resource-greedy and inefficient. As the result, BIST techniques are often based on pseudo-random pattern generators (PRPG), which represent simple structures that can generate necessary test stimuli for a device under test (DUT). A typical example of such an embedded test generator that is widely used in testing and diagnosis of contemporary complex electronic systems is a Linear Feedback Shift Register (LFSR).

Figure 1.

Internal structure of LFSR; the sequence it generates

In Figure 1, a common internal structure of LFSR is shown. It consists of D flip-flops connected in series and feedback loops collected by an XOR gate. This forms a simple shift register with a special sort of feedback. The presence or absence of the feedback loops is described by a so-called generator polynomial. Each flip-flop in LFSR has a corresponding term in this polynomial – accordingly to their order in the shift register. The constant at each term is either 0 or 1 depending on the presence or absence of the corresponding feedback loop. The last term in the polynomial is always 1 and has no matching feedback. The polynomial shown in Figure 1, hence, has four terms x5, x4, x, and 1.

The state of the LFSR at the beginning of test generation is determined by its initial state parameter called seed. Hence, the seed and polynomial fully predetermine the resulting sequence and therefore have direct influence on the resulting test quality and, therefore, they play an important role in TPG.

It is the main useful property of LFSR circuits that being clocked repeatedly, they go through a fixed sequence of unique states, which has a number of explicit properties of randomness and can be used, therefore, as a TPG in a BIST scheme (Crouch, 1999; Bushnell & Agrawal, 2000). The maximum number of such unique states is (2n – 1), where n is the length of the LFSR (i.e. the number of flip-flops). However, in most cases the effective length of such sequence is much shorter. Hence, in most of modern approaches, a fully configured LFSR is used. Its configuration is based on a primitive polynomial – a polynomial that guarantees (2n – 1) unique states for an arbitrary seed, except the all-zero state. Figure 1 shows an example of configured LFSR, the seed, and the resulting sequence. One can see that the sequence has 4 unique patterns (the grey part is just a repetition of the black one). Hence, the polynomial used in this example is not a primitive one.

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