Simulations and Modeling of TFET for Low Power Design

Simulations and Modeling of TFET for Low Power Design

Sunil Kumar (Dr. B. R. Ambedkar NIT Jalandhar, India) and Balwinder Raj (NIT Jalandhar, India)
DOI: 10.4018/978-1-4666-8823-0.ch021
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Abstract

In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).
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Introduction

With the continued miniaturization of MOSFETs, the OFF-state leakage current (IOFF) is exponentially increasing with reduction of the threshold voltage imposed by the fundamental limit to 60 mV/decade subthreshold swing at room temperature (Singh, Ramakrishnan, Mookerjea, Datta, Vijaykrishnan, & Pradhan, 2010). This limits the on current (ION) and the ION-IOFF ratio severely as the supply voltage is reduced. To overcome these problems, new engineering solutions like improving the structure of the device, considering different materials with various features (Si, SiGe, Ge, etc) in the channel region and new dielectric (high-k) are suggested which are being used for a better exploitation of these devices (Kamali, Moghaddam, & Hosseini, 2012). In recent years, there are many novel nanoscale semiconductor devices such as DG MOSFET, FinFET, Gate-All-Around (GAA), Tunnel FET etc. studied to obtain a minimum IOFF and a maximum ratio of ION/IOFF as well as high ON current to avoid these limitations.

Tunnel FETs (TFETs) are today being intensively investigated (Zhang, Zhao, & Seabaugh, 2006) as some of the most promising devices that would allow logic circuit operation voltages below 0.5 V and reduced static power consumption. These features are conceivable owing to the possibility of achieving sub-threshold switching slopes (<60 mV/decade) at room temperature, due to Band-To-Band Tunneling (BTBT) in gated reverse-biased p–i–n junctions (Choi, Park, Lee, & Liu, 2007). Transistors which use BTBT to inject carriers into the channel instead of injecting carriers over a barrier are not limited by 60 mV/decade turn-off (Kim, Kam, Hu, & Liu, 2009). These tunneling transistors (TFETs) are therefore of great interest for high ION/IOFF at low voltages. TFET performance is limited by the BTBT generation rate which is exponentially dependent on the effective tunneling bandgap as well as effective carrier mass of the semiconductor (Sze & Ng, 2007). The obvious means to enhance TFET performance and scale VDD is by scaling this effective tunneling bandgap. This can be achieved by moving from Si to Ge to even lower bandgap III-V materials (Ionescu, Boucart, Moselund, Pott, & Tsamados, 2007). Since low IOFFkeeps the standby power consumption low, a TFET with lowest IOFFand largest ION/IOFFat a reduced VDD is desired for ultra-low voltage operation. Among the most studied and optimized TFETs architectures, thin film Double-Gated (DG) lateral p–i–n TFET (Boucart & Ionescu, 2007) and a p-i-n TFET with a delta-doped n+ at the source side are shown to offer remarkable for obtained high ION/IOFF ratio and good output characteristics. (Kamali, Moghaddam, & Hosseini, 2012), (Krishnamohan, Kim, Raghunathan, & Saraswat, 2008).

Key Terms in this Chapter

Punch-Through: It a break down mechanism, punch-through occurs when the depletion region, around the drain touches to the source region, causing current to flow irrespective of gate voltage at high drain bias positive voltage.

Drain Induced Barrier Lowering (DIBL): In short channel devices, the reduction of threshold voltage, and resulting the subthreshold current vary with higher drain bias called as DIBL.

Zener Tunneling: It is a reverse breakdown mechanism in which high electric field generated at P-N junction, electrons tunnel from the valence band to conduction band of a semiconductor device.

Scaling: Reduction in feature size of MOSFETs device.

EOT (Equivalent Oxide Thickness): It determines how much thick (nanometer) of silicon oxide film (SiO 2 ) would be required to induce the same effect as the high-k material being used.

Short-Channel Effects: The effective channel length is equal to the order of magnitude as thickness of the body of the device.

Delta-Doped: It is a properties of doping distribution in semiconductor to get thin layers of high dopant concentration within spatial limit which is grown by MOCVD technique.

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