Testing complex systems on a chip (SoCs) with up to billions of transistors has been a challenge to IC test technology for more than a decade. Most of the research work in IC test technology has focused on problems of production testing, while the problem of self test in the field of application has found much less attention. With SoCs being used also in long-living systems for safety critical applications, such enhanced self test capabilities become essential for the dependability of the host system. For example, automotive electronic systems must be capable of performing a fast and effective start-up self test. For future self-repairing systems, fault diagnosis will become necessary, since it is the base for dedicated system re-configuration. One way to solve this problem is a hierarchical self-test scheme for embedded SoCs, based on hardware and software. The core of the test architecture then is a test processor device, which is optimised to organize and control test functions efficiently and at minimum cost. This device must be highly reliable by itself. The chapter introduces the basic concept of hierarchical HW / SW based self test, the test processor concept and architecture, and its role in a hierarchical self test scheme for SoCs.
TopBackground
Testing large-scale integrated „Systems on a Chip“ (SoCs) has been a problem since their arrival in the 1990s (Design and Test Roundtable, 1997 & 1999, Zorian, Y., Marinissen, E. J. & Dey, S., 1998). Not only the complexity of SoCs has created problems, but also their heterogeneous structure. Although an SoC does not incorporate embedded processors by definition, real systems of such kind will usually consist of one or more processor cores, memory blocks, logic blocks, often also analog and mixed-signal functional blocks, and, to some extent, even radio frequency (RF) devices. SoCs containing multiple processor cores, so-called MP-SoCs, are the core of all hand-held communication devices. Typically, such complex systems are operated in a “locally synchronous – globally asynchronous” mode, also including a complex communication scheme based on multiple buses, bridges and bus couplers. A typical structure is shown in figure 1.
Figure 1. Structure of a multiple processor system on a chip (MP-SoC)
Unlike application specific ICs (ASICs), MP-SoCs will always have their functionality mainly defined by “embedded” software. Already this feature limits their functional testability by conventional methods. Even worse, a semiconductor manufacturer, who does not have the software that will later on run on the system, will not be able to perform a comprehensive functional test. Furthermore, embedded hardware blocks will often be imported as pre-designed “components off the shelf” (COTS) or as IP (intellectual property) blocks, whose real structure may even be unknown to the system designer. Then testing is usually based on a set of patterns delivered by the IP-block vendor. How such patterns can be applied to the embedded block has been a matter of research for some time (see chapters on SoC testing elsewhere in this book).
Within a specific IEEE working group, innovative test technology for SoCs has been developed since the 1990s (Zorian, Y., 1997, Zorian, Y., Marinissen, E. J. & Dey, S., 1998, Goel, S. K.& Marinissen, E. J., 2002). The basic concept developed there consists of test-supporting extra circuitry around embedded blocks, so-called wrappers, and additional test access channels. By such means, test access for functional testing of embedded blocks or even for structure-oriented tests is facilitated.