Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization

Synthesis of Analog Circuits by Genetic Algorithms and their Optimization by Particle Swarm Optimization

Esteban Tlelo-Cuautle, Ivick Guerra-Gómez, Carlos Alberto Reyes-García, Miguel Aurelio Duarte-Villaseñor
DOI: 10.4018/978-1-60566-798-0.ch008
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This chapter shows the application of particle swarm optimization (PSO) to size analog circuits which are synthesized by a genetic algorithm (GA) from nullor-based descriptions. First, a historical description of the development of automatic synthesis techniques to design analog circuits is presented. Then, the synthesis of analog circuits by applying a GA at the transistor level of abstraction is demonstrated. After that, the authors present the proposed multi-objective (MO) PSO algorithm which makes calls to the circuit simulator HSPICE to evaluate performances until optimal sizes of the transistors are found by using standard CMOS technology of 0.35µm of integrated circuits. Finally, the MO-PSO algorithm is compared with NSGA-II, and some open problems oriented to circuit synthesis and sizing are briefly discussed.
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Recently, some research on the application of evolutionary algorithms has been conducted to synthesize practical electronic circuits. As mentioned by Koza et al. (2004), Liu et al. (2009), and Mattiussi and Floreano (2007), many electronic systems of technical and scientific interest can be seen as collections of devices connected by links characterized by a numeric value. Furthermore, the synthesis or design of analog circuits can be viewed as the focus of the engineering activity (Martens and Gielen, 2008; McConaghy and Gielen, 2006; Tlelo-Cuautle and Duarte-Villaseñor, 2008a; Unno and Fujii, 2007). In electronics, an analog designer has several design strategies at his disposal to synthesize electronic circuits (Eeckelaert et al., 2005; Koza et al., 2004; Mattiussi and Floreano, 2007; McConaghy et al., 2005; Rutenbar et al., 2007; Smedt and Gielen, 2003; Stehr et al., 2007; Tlelo-Cuautle and Duarte-Villaseñor, 2008a; Van der Plas et al., 2001). However, as mentioned by Martens and Gielen (2008), the chosen strategy mainly depends on the complexity of the system with respect to size and performance demands (Guerra-Gómez et al., 2008). On the other hand, the design process starts with the selection of a topology, where systematic exploration methodologies are very much needed to automatically generate new topologies (McConaghy et al., 2007; Rutenbar et al., 2007; Smedt et al., 2003; Tlelo-Cuautle and Duarte-Villaseñor, 2008a). Afterwards, for a selected topology, the next problem consists of searching different values for the parameters until optimal performances are found. Although Stehr et al. (2007) presented a simulation-based method for the calculation of the feasible performance values of amplifier-based circuits by computing the Pareto-optimal trade-offs of competing performances at full simulator accuracy, there are new circuits which include multi-ports, such as current conveyors (Fakhfakh et al., 2007; Sánchez-López et al., 2007; Smith and Sedra, 1968; Tlelo-Cuautle et al., 2008c; Trejo-Guerra et al., 2008) which also present trade-offs among their port's characteristics. Therefore an appropriate optimization method must be used to find optimal parameters for a particular circuit topology.

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