Synthesis of LC-Oscillators Using Rival Multi-Objective Multi-Constraint Optimization Kernels

Synthesis of LC-Oscillators Using Rival Multi-Objective Multi-Constraint Optimization Kernels

Ricardo Póvoa (Instituto de Telecomunicações, Portugal & Universidade de Lisboa, Portugal), Ricardo Lourenço (Universidade de Lisboa, Portugal), Nuno Lourenço (Instituto de Telecomunicações, Portugal & Universidade de Lisboa, Portugal), António Canelas (Instituto de Telecomunicações, Portugal & Universidade de Lisboa, Portugal), Ricardo Martins (Instituto de Telecomunicações, Portugal & Universidade de Lisboa, Portugal) and Nuno Horta (Instituto de Telecomunicações, Portugal & Universidade de Lisboa, Portugal)
DOI: 10.4018/978-1-4666-6627-6.ch001
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This chapter presents a state-of-the-art multi-objective/multi-constraint design automation approach applied to the design of an LC-Voltage Controlled Oscillator and an LC-Oscillator for a 130 nm technology node and leading to sets of design solutions showing figures-of-merit around -192 dBc/Hz and -186 dBc/Hz, respectively. The proposed approach, implemented in AIDA-C, guarantees accuracy by using commercial circuit simulators (HSPICE® and ELDO®) to evaluate the performance of the tentative circuit solutions, where the number of time-consuming circuit simulations is efficiently pruned by the optimization kernel. Three multi-objective optimization algorithms, the NSGA-II, the MOPSO, and the MOSA, are experimented with in the synthesis of the quoted oscillators and compared in terms of performance using statistical results obtained from multiple synthesis runs for each one of the oscillators. The performance of the optimized oscillators is then compared to other state-of-the-art results, showing the benefits of the presented multi-objective design approach.
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The steady growth of the digital consumer wireless communications market, while the communications standards are becoming more complex, drives the design of low cost and high performance receivers, transmitters and transceivers, leading to requirements for analog and Radio-Frequency (RF) circuit performance figures such as noise, linearity and power consumption, that are at the edges of what is technologically possible. This forces RF integrated circuit designers to explore design tradeoffs to the limit for each circuit, making the design process long and expensive, with impact on the time to market and on the price of the final products. Integrated oscillators are among such RF circuits, and are key components for wireless communications circuits (e.g. Bluetooth, WI-FI or CDMA) (Rout, Nanda, Acharya & Panda, 2012).

In general, the design of oscillators is done aiming at minimizing both phase noise and power consumption for a given oscillation frequency, to compensate the degradation of the on-chip LC tank quality factor, while satisfying the continuously growing need for power-efficiency. However, when low power consumption is desired, the biasing current tends to be small, leading to a larger impact of the parasitic effects in the circuit, increasing the phase noise. On the other hand, to have a low phase noise, a high output voltage swing is desired, which commonly leads to an increase of the power consumption.

These conflicting objectives are reflected in the Figure-of-Merit (FOM) defined by Kinget (1999) and shown in (1), where ω0 is the oscillation frequency, Pdc is the power consumption, Δω is the offset from the output frequency and Lω) is the oscillator phase noise, given by (2), the original Leeson’s (1966) equation, where Q is the loaded quality factor of the oscillator, k is the Boltzmann’s constant, T is the absolute temperature, Psig is the oscillation output power, F is the noise factor of the amplifier and Δω1/f3 is the corner frequency between ω1/f2 and ω1/f3 portion of the phase noise spectrum (Lee, 1998). Finally, the more negative the value of the figure-of-merit (or higher absolute value), the better the performance of an oscillator.


In this chapter, the phase noise versus power consumption design tradeoff is explored with the application of a multi-objective optimization approach to the design of integrated oscillators, where multiple constraints are ensured to guarantee functional circuits. A design automation methodology for analog IC circuit-level synthesis and optimization, considering three rival Multi-Objective (MO) optimization methods, namely the MO Particle Swarm Optimization (MOPSO) (Reyes-Sierra & Coello, 2006), the MO Simulated Annealing (MOSA) (Bandyopadhyay, & Saha, 2013) and the Non-dominated Sorting Genetic Algorithm II (NSGA-II) (Deb, Pratap, Agarwal, & Meyarivan, 2002), is presented and evaluated. The accuracy and reliability of the attained solution is guaranteed by using commercial circuit simulators and device models from industry technology nodes. The circuit optimization tool, AIDA-C, implements the proposed approach and was here used for the automatic synthesis of two resonant oscillator circuits (an LC–Voltage Controlled Oscillator (LC-VCO) and an LC-Oscillator). Finally, the advantages of such a multi-objective approach to the design of these oscillators are shown, comparing the performance of the optimized solutions with results published by other authors.

This chapter is organized as follows: first, a brief background on the considered oscillator circuits and the latest design techniques of high performance integrated resonant oscillators is provided. Then, the proposed multi-objective multi-constraint methodology for sizing and optimization implemented in AIDA-C is described. The results of the multi-objective optimization of the two oscillator circuits are then presented and analyzed. Finally, the conclusions are drawn.

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