Systematic Design Principles for Cost-Effective Hard Constraint Management in Dynamic Nonlinear Systems

Systematic Design Principles for Cost-Effective Hard Constraint Management in Dynamic Nonlinear Systems

Satyakiran Munaga (IMEC and K. U. Leuven/ESAT, Belgium) and Francky Catthoor (IMEC and K. U. Leuven/ESAT, Belgium)
Copyright: © 2013 |Pages: 28
DOI: 10.4018/978-1-4666-2056-8.ch001
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Abstract

Modern cost-conscious dynamic systems incorporate knobs that allow run-time trade-offs between system metrics of interest. In these systems regular knob tuning to minimize costs while satisfying hard system constraints is an important aspect. Knob tuning is a combinatorial constrained nonlinear dynamic optimization problem with uncertainties and time-linkage. Hiding uncertainties under worst-case bounds, reacting after the fact, optimizing only the present, and applying static greedy heuristics are widely used problem simplification strategies to keep the design complexity and decision overhead low. Applying any of these will result in highly sub-optimal system realizations in the presence of nonlinearities. The more recently introduced System Scenarios methodology can only handle limited form of dynamics and nonlinearities. Existing predictive optimization approaches are far from optimal as they do not fully exploit the predictability of the system at hand. To bridge this gap, the authors propose the combined strategy of dynamic bounding and proactive system conditioning for the predicted likely future. This paper describes systematic principles to design low-overhead controllers for cost-effective hard constraint management. When applied to fine-grain performance scaling mode assignment problem in a video decoder design, proposed concepts resulted in more than 2x energy gains compared to state-of-the-art techniques.
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Introduction

Highly Dynamic Electronic Systems

Modern electronic systems are highly dynamic with multiple sources of dynamism including user, environment, hardware, input data, and mapping. At hardware implementation level, manufacturing process variability and material degradation are the two most-worried sources in advanced nanoscale device and 3D integration technologies (Borkar, 2005; Groeseneken, 2005; Srinivasan et al., 2004) - they will result in spatial and temporal variation in parametric behavior (such as delay/access-time, active and leakage power) of components (such as functional units, memories, and communication links) (Groeseneken, 2005; Papanicolaou et al., 2008). They can also lead to temporary or permanent unavailability of a whole component or some operational modes of the component. These variations are traditionally hidden under worst-case abstractions (e.g., static clock period and functional failure) and made invisible to higher abstraction levels (typically by using simple redundancy-based techniques (Srinivasan et al., 2005; Constantinides et al., 2006)). With appropriate circuit-level techniques, such as delayed clocking (Ernst et. al., 2003) and measurement-driven adaptation, this dynamism can be propagated through the abstraction layers and made visible to higher levels leading to, what we call, dynamic hardware interface.

Next to this, user inputs (e.g., changing from GPS navigation to video streaming application and changes in quality-of-service requirements such as frame rate, resolution, and level-of-detail) result in a dynamically changing set of applications, algorithms and their workload (Tack et al., 2005). In other words, sharing platform resources among multiple dynamic applications/tasks results in dynamic changes in the resource availability for a given application or task-set. Smart algorithms of future systems which adapt themselves to environment changes (e.g., moving from a WiFi hotspot area to WiMax/3G coverage area, fluctuating wireless channel state due to fading effects, changing requirements of dynamic active set of users sharing the same frequency spectrum) result in a dynamic workload (Li et al., 2008). In applications like video codec and graphics rendering, input data being processed by the algorithm results in varying workload both within and across the frames (Wiegand et al., 2003). Cost-efficient mapping (e.g., bit-width aware compilation, distributed loop-buffers, etc) of algorithms on architectures further exploits the variations in the control and data signals and thus acts as additional source of dynamism (typical compilation techniques hide this dynamism with abstractions such as worst-case bit-width and predication) (Novo et al., 2008). Although the dynamism introduced by mapping is significantly influenced by other sources of dynamism, its complexity and huge impact on optimality make it worth treating as a separate source.

To summarize, both the physical components of the system (so-called hardware) and their usage (so-called software) are extremely dynamic in most modern system contexts (as conceptually shown in Figure 1). It is important that the system allows the exploitation of dynamism by having not so large load-independent cost as shown in Figure 2. Today many platforms are not designed to expose the underlying true cost variations. This implies the application designers have to discover the hidden opportunity to push the platform designers towards alternative holistically optimal systems. Similarly we assume that platforms suitable for hard constrained dynamic systems typically incorporate features to enable deterministic application mapping (like software controlled memories, time multiplexed access of shared resources, etc.) (Bekooij et al., 2004).

Figure 1.

Multi-pronged dynamism in modern system contexts

Figure 2.

Platforms with large load-independent cost are not fit for exploiting dynamism as there is nothing much to gain from adapting the system to the dynamic situation at hand

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