TopThe Basic Principle
SPI communication consists of a so-called master and one or more slaves. The master is the communication end that drives the clock line in order to exchange data with the slave. Figure 1 shows a simple configuration depicting only one slave. When the master decides to communicate with the slave, it asserts the Slave Select 
pin. Consequently, the slave leaves the high-impedance state and becomes electrically connected to the serial bus. Upon writing a byte to the master’s transmit register, an internal shift register pops out these bits one at a time starting with the MSB. The bits transferred from the master on SDO (Serial Data Out) or MOSI (Master Output Slave Input) will in turn “kick-out” the bits residing in the slave’s shift register (see Figure 2). The bits out of the slave appear on the master’s SDI (Serial Data In) or MISO (Master Input Slave Output). In brief, the shift registers of both the master and the slave act like one circular shift register.
Figure 1. Master/slave connection between 2 PIC18F25K22 processors
Although the master always initiates data transfer, communication between the master and the slave may take one of the following forms:
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The master sends a dummy byte to the slave. In return, the slave pops out data residing in its shift register. This data is received by the master. The slave may be an analog-to-digital converter (or any other input device) with serial interface. Such a configuration requires the SCK line between master and slave to be connected. The MOSI line becomes redundant and may be disconnected.
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The master sends useful data to the slave which in turn ejects a dummy byte from its shift register. This configuration is applicable whenever the slave is an output device such as a digital-to-analog converter. No physical connection of the MISO line between master and slave is required in this case.
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The master and slave exchange data between each other. A typical example consists of two MCUs, a master and a slave, communicating in full-duplex mode. Obviously, this requires both SDO and SDI to be connected between the master and the slave.
Figure 2. Internal hardware (simplified) of the master and the slave
As to the data format or position of the data bits with respect to the clock edge, it is the master’s responsibility to setup the appropriate configuration in accordance with the peripheral device connected to the bus. The rule of thumb is simple: if the slave latches the data at the rising edge of the clock, the master must output the data bits at the falling edge and vice versa. One may also need to control the clock rate to match the rate of the slave device. The control registers in charge of setting up the clock polarity/phase and the bit rate are covered in the section ‘Control Registers’.