The Switched Local Area Networks’ Delay Problem: Issues and a Deterministic Solution Approach

The Switched Local Area Networks’ Delay Problem: Issues and a Deterministic Solution Approach

Monday O. Eyinagho (Covenant University, Nigeria) and Samuel O. Falaki (Federal University of Technology Akure, Nigeria)
DOI: 10.4018/978-1-4666-2208-1.ch003
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A large number of installed local area networks are sluggish in terms of speed of uploading and downloading of information. Researchers have, therefore, proposed the need for such networks to be designed with specified maximum end-to-end delay. This is because, if the maximum packet delay between any two nodes of a network is not known, it is impossible to provide a deterministic guarantee of worst case response times of packets’ flows. Therefore, the need for analytic and formal basis for designing such networks becomes very imperative. In this regard, this chapter has discussed the switched local area networks’ delay problem and related issues. It compared the two principal approaches for determining the end-to-end response times of flows in communication networks – stochastic approach and deterministic approach. The chapter goes on to demonstrate the superiority of the latter approach by using it to develop and validate the goodness of a general maximum delay packet switch model.
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The Delays In Computer Networks

One fundamental characteristics of a packet-switched network is the delay required to deliver a packet from a source to a destination. (Bolot, 1993) Each packet generated by a source is routed to the destination via a sequence of intermediate nodes; the end-to-end delay is, thus, the sum of the delays experienced at each hop on the way to the destination. (Bolot, 1993) Each such delay in turn consists of two components (Ming-Yang et al., 2004; Bolot, 1993; Bertsekas and Gallager, 1992, p. 150);

  • 1.

    A fixed component which includes:

    • a.

      The transmission delay at the node,

    • b.

      The propagation delay on the link to the next node,

  • 2.

    A variable component which includes:

    • a.

      The processing delay at the node,

    • b.

      The queuing delay at the node.

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