Thermal Analysis of the MIPS Processor Formulated within DEVS Conventions

Thermal Analysis of the MIPS Processor Formulated within DEVS Conventions

Alejandro Moreno Astorga (Universidad Nacional de Educación a Distancia, Spain), José L. Risco-Martín (Universidad Complutense de Madrid, Spain), Eva Besada-Portas (Universidad Complutense de Madrid, Spain), Luís de la Torre (Universidad Nacional de Educación a Distancia, Spain) and Joaquín Aranda (Universidad Nacional de Educación a Distancia, Spain)
DOI: 10.4018/978-1-4666-4369-7.ch004
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Abstract

The MIPS processor is used in computer architecture courses in order to explain matters such as performance analysis, energy consumption, and reliability. Currently, due to the desire for more powerful computers, it is interesting to learn how to reallocate certain components in order to achieve heat reduction with low cooling costs. DEVS is a general formalism for modeling and analysis of discrete event systems based on set theory and represents a basis for discrete event abstractions by formalizing the concept of activity which relates to the specification and heterogeneous distribution of events in space and time. The MIPS simulator is built upon known techniques for discrete event simulation and its definition within a formal language such as DEVS provides completeness, verifiability, extensibility, and maintainability. In this chapter, the authors carry out a thermal analysis of the MIPS processor using a DEVS simulator and show a register reallocation policy based on evolutionary algorithms that notably decreases the resulting register bank temperature.
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Mips

MIPS (acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32 and MIPS64 define a control register set as well as the instruction set. From now on we will refer to MIPS architecture as the MIPS32 revision.

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