High temperature has become a technological barrier to the testing of high performance systems-on-chip, especially when deep submicron technologies are employed. In order to reduce test time while keeping the temperature of the cores under test within a safe range, thermal-aware test scheduling techniques are required. In this chapter, the authors address the test time minimization problem as how to generate the shortest test schedule such that the temperature limits of individual cores and the limit on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, the authors partition test sets into shorter test sub-sequences and add cooling periods in between, such that applying a test sub-sequence will not drive the core temperature going beyond the limit. Furthermore, based on the test partitioning scheme, the authors interleave the test sub-sequences from different test sets in such a manner that a cooling period reserved for one core is utilized for the test transportation and application of another core. The authors have proposed an approach to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods as well as alternative test schedules. Experimental results have shown the efficiency of the proposed approach.
TopIntroduction
Nanoscale technology has become the mainstream in the design and production of integrated circuits (ICs). In the latest generation of IC designs, the power density has been substantially increased (Borkar, 1999), (Gunther, Binns, Carmean, & Hall, 2001). As a consequence of the elevated power density, high temperature in the chip becomes a critical challenge (Skadron et al., 2004), (Mahajan, 2002). In particular, compared to the normal functional mode, testing consumes more power (Pouya & Crouch, 2000), (Shi & Kapur, 2004), leading to an even higher temperature on silicon dies. Therefore, temperature control during test is required in order to avoid damages to the circuits under test. Some advanced cooling techniques are proposed to reduce the temperature of ICs, but they substantially increase the overall cost. Other techniques, such as lower frequency and reduced speed, can partly solve the high temperature problem, while making them inapplicable to at-speed test and leading to longer test application time (TAT).
In the case of system-on-chip (SoC) test, the problems of long test time and high temperature become more severe. Due to the high power consumption and high temperature in the latest generation of SoCs, novel techniques are proposed to tackle the problem of long test time. In (Rosinger, Al-Hashimi, & Nicolici, 2004), (Girard, Landrault, Pravossoudovitch, & Severac, 1998), low-power test techniques are proposed to reduce the power consumption during tests. Some other works focus on power-constrained test scheduling (Chou, Saluja, & Agrawal, 1997), (Larsson & Peng, 2006), (Chakrabarty, 2000), (He, Peng, & Eles, 2006), targeting test time minimization restricted in a fixed power envelope. However, only using the power-aware techniques cannot fully avoid the overheating problem because of the complex thermal phenomenon in modern ICs (Rosinger, Al-Hashimi, & Chakrabarty, 2006).
Recently, thermal-aware test techniques have been proposed in order to solve the overheating problem during SoC tests. Liu et al. proposed a technique (Liu, Veeraraghavan, & Iyengar, 2005) to evenly distribute the generated heat across the chip during tests, and as a result, avoid high temperature. Rosinger et al. proposed an approach (Rosinger et al., 2006) to generate thermal-safe test schedules that minimizes the test application time and reduces temperature variation across the silicon die, utilizing the information of core adjacency. In (Yu, Yoneda, Chakrabarty, & Fujiwara, 2007), Yu et al. addressed the thermal-safe TAM/wrapper co-optimization problem and proposed a test scheduling approach to generate efficient test schedules. Although these proposed approaches generate efficient test schedules, they make strong and simplifying assumption that a core under test is never overheated during the application of a single test set. In this chapter, we address the test time minimization problem for system-on-chip test with thermal awareness. We assume that applying a single test set to a core may raise the temperature of the core under test and exceed a temperature limit beyond which the core may be damaged. In order to generate thermal-safe test schedules and at the same time minimize the test time, we propose a test set partitioning and interleaving (TSPI) technique. Based on the proposed TSPI technique, we propose a heuristic-based approach (He, Peng, & Eles, 2007) which explores alternative test set partitioning and interleaving schemes in which partitions and cooling periods have arbitrary lengths.