Validation and Verification

Validation and Verification

Copyright: © 2017 |Pages: 23
DOI: 10.4018/978-1-5225-2303-1.ch007
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Introduction

In last chapter, we introduced simulation techniques that are used in testing. In this chapter we will talk about verification and validation for which we apply these simulation techniques along with other methods to test requirements, design and implementation.

Verification is the process of evaluating design artifacts of a development phase to determine whether they meet the specified requirements for that phase. Verification is performed to ensure that the design artifacts meet their specified requirements. Design artifacts include requirement specifications, design documents, code, and test cases. It asks the question: “Are we building the product right?”

Validation is the process of evaluating final product, system or system component during or at the end of the development cycle to determine whether it meets specified business requirements. It is performed to ensure that the product actually meets the user’s needs and that the specifications were correct in the first place; in other words, to demonstrate that the product fulfills its intended use when placed in its intended environment. It asks the question: “Are we building the right product?” It is performed on actual product or software by testing. It is entirely possible that a product passes verification but fails validation. This happens when a product is built as per the specifications but the specifications themselves fail to address the user’s needs.

Verification and validation is applied throughout the development process and enables you to find errors before they can find a way into the next development phase or the final product. Most system design errors are introduced in the original specification, but aren't found until the test phase. When engineering teams use models to perform virtual testing or real-time testing early in the development cycle, they discover and eliminate problems and reduce development time by as much as 50%. Verification and validation should be systematically performed across all design artifacts including requirements, model, code, and the final embedded system (Figure 1).

Figure 1.

Model-based control design verification and validation workflow

Early Requirements Validation

You can uncover incorrect, inconsistent, and missing requirements and design flaws early by simulating system behavior to validate requirements and by specifying system design properties that guarantee functional behavior. This can be done by creating high-level system models and running simulations. A high-level system model is a functional model without implementation details. You can gain further insight into system behavior through simulation by creating a system model that includes the control algorithm or software model and the physical plant and environmental models of your system. This system model is associated with system requirements to analyze and validate requirements early in the development process.

You write system-level tests and link them to requirements. You define key test scenarios and document and systematically analyze system behavior captured in the system model simulation. Analysis results provide early feedback on the completeness and integrity of requirements and can be used to define expected behavior of the algorithm or software model for further design refinement. You explore the entire design parameter space in simulation to help select those tests that are critical to run on real-time targets or real-world hardware. Requirements traceability to design helps manage change and reduce waste in the design lifecycle.

Through requirement validation you can iteratively refine requirements and refine design properties. Formal methods can be applied to analyze models to improve your designs and reveal unanticipated functionality that would be difficult to uncover by simulation alone.

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