Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

Alessandro Strano (Intel Mobile Communications, Germany), Carles Hernández (Barcelona Supercomputing Center, Spain), Federico Silla (Universitat Politècnica de València, Spain) and Davide Bertozzi (Università degli studi di Ferrara, Italy)
DOI: 10.4018/978-1-4666-6034-2.ch016


In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.
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Many recent works analyze the impact of process variations on the performance of integrated circuits, providing data on how parameter variations impact the maximum design frequency (Bowman, 2002) or variability models that characterize variations in microarchitecture (Sarangi, 2008; Bonesi, 2008). However, these studies do not consider the implications of variations in the interconnect infrastructure. Although (Nicopoulos, 2010) is a step forward in this direction, this study neglects the impact of manufacturing deviations on NoC links. Unfortunately, this impact is not negligible (Mondal, 2007; Hernández, 2010; Hassan, 2009). On one hand, although there are examples of repeater-less NoC self-calibrating links (Jose, 2005), they typically undergo repeater insertion. Therefore, they suffer from Lgate variations and dopant fluctuations in the transistors building up repeater stages, and also suffer from the variability introduced by the chemical metal planarization process (Mondal, 2007).

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