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What is Cell Broadband Engine Architecture

Handbook of Research on Scalable Computing Technologies
Cell Broadband Engine Architecture, also abbreviated CBEA or Cell/B.E. or called Cell as a shorthand, is a microprocessor architecture jointly developed by Sony, Toshiba, and IBM. It is a heterogeneous multi-core architecture by combining one general-purpose Power architecture core PPE (Power Processor Element) with eight streamline coprocessing elements SPEs (Synergistic Processor Elements). PPE supports the operating system and is mainly used for control tasks. SPEs support SIMD (Single Instruction Multiple Data) processing. Each SPE has 128 entries 128-bit registers and 256KB local memory (called local storage) both for instructions and data. The PPE, SPEs and memory subsystem are connected by on-chip bus Element Interconnect Bus (EIB). Cell is designed as a general-purpose high-performance processor to bridge the gap between conventional desktop processors and more specialized high-performance processors. It has been installed in Sony PlayStation 3.
Published in Chapter:
Cell Processing for Two Scientific Computing Kernels
Meilian Xu (University of Manitoba, Canada), Parimala Thulasiraman (University of Manitoba, Canada), and Ruppa K. Thulasiram (University of Manitoba, Canada)
Copyright: © 2010 |Pages: 25
DOI: 10.4018/978-1-60566-661-7.ch014
Abstract
This chapter uses two scientific computing kernels to illustrate challenges of designing parallel algorithms for one heterogeneous multi-core processor, the Cell Broadband Engine processor (Cell/B.E.). It describes the limitation of the current parallel systems using single-core processors as building blocks. The limitation deteriorates the performance of applications which have data-intensive and computationintensive kernels such as Finite Difference Time Domain (FDTD) and Fast Fourier Transform (FFT). FDTD is a regular problem with nearest neighbour comminuncation pattern under synchronization constraint. FFT based on indirect swap network (ISN) modifies the data mapping in traditional Cooley- Tukey butterfly network to improve data locality, hence reducing the communication and synchronization overhead. The authors hope to unleash the Cell/B.E. and design parallel FDTD and parallel FFT based on ISN by taking into account unique features of Cell/B.E. such as its eight SIMD processing units on the single chip and its high-speed on-chip bus.
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