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What is Dynamic Partial Reconfiguration (DPR)

Handbook of Research on Embedded Systems Design
A feature in the FPGA where a a portion of an FPGA device can be reconfigured while the device is still operating.
Published in Chapter:
Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems
Naim Harb (Polytechnic Faculty of Mons, Belgium), Smail Niar (LAMIH-University of Valenciennes Le Mont Houy, France), and Mazen A. R. Saghir (Texas A&M University at Qatar, Qatar)
Copyright: © 2014 |Pages: 25
DOI: 10.4018/978-1-4666-6194-3.ch014
Abstract
Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.
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