In semiconductor manufacture, one way of accounting for uncertainty in the design and manufacturing process is to weaken the guarantees on certain design criteria (such as power consumption or minimum clock speed). This weakening creates a ‘margin of error’ known as a guardband.
Published in Chapter:
Designing Resource-Constrained Embedded Heterogeneous Systems to Cope with Variability
Ian Gray (University of York, UK), Andrea Acquaviva (Politecnico di Torino, Italy), and Neil Audsley (University of York, UK)
Copyright: © 2014
|Pages: 27
DOI: 10.4018/978-1-4666-6194-3.ch004
Abstract
As modern embedded systems become increasingly complex, they also become susceptible to manufacturing variability. Variability causes otherwise identical hardware elements to exhibit large differences in dynamic and static power usage, maximum clock frequency, thermal resilience, and lifespan. There are currently no standard ways of handling this variability from the software developer's point of view, forcing the hardware vendor to discard devices that fall below a certain threshold. This chapter first presents a review of existing state-of-the-art techniques for mitigating the effects of variability. It then presents the toolflow developed as part of the ToucHMore project, which aims to build variability-awareness into the entire design process. In this approach, the platform is modelled in SysML, along with the expected variability and the monitoring and mitigation capabilities that the hardware presents. This information is used to automatically generate a customised variability-aware runtime, which is used by the programmer to perform operations such as offloading computation to another processing element, parallelising operations, and altering the energy use of operations (using voltage scaling, power gating, etc.). The variability-aware runtime affects its behaviour according to modelled static manufacturing variability and measured dynamic variability (such as battery power, temperature, and hardware degradation). This is done by moving computation to different parts of the system, spreading computation load more efficiency, and by making use of the modelled capabilities of the system.