What is Hardware Description Language

This chapter presents the design and development of a hardware based architecture of Evolutionary Algorithm for solving both the unimodal and multimodal fixed point real parameter optimization problems. Here a modular architecture has been proposed to provide a tradeoff between real time performance and flexibility and to work as a resource efficient reconfigurable device. The evolutionary algorithm used here is Genetic Algorithm. Prototype implementation of the algorithm has been performed on a system-on-chip field programmable gate array. The notable feature of the architecture is the capability of optimizing a wide class of functions with minimum or no change in the synthesized hardware. The architecture has been tested with ten benchmark problems and it has been observed that for different optimization problems the synthesized target requires maximum of 5% logic slice utilization, 2% of the available block RAMs and 2% of the DSP48 utilization in Xilinx Virtex IV (ML401, XC4VLX25) board.